Non-volatile memory device, operating method thereof, controller for controlling the same, and storage device including the same

Abstract

An operating method of a storage device includes reading a wear-out pattern of a memory block when a controller determines the memory block is a re-use memory block of a non-volatile memory device; selecting an operation mode corresponding to the read wear-out pattern using the controller; and transmitting the selected operation mode to the non-volatile memory device using the controller.

What is claimed is: 
     
         1 . A non-volatile memory device, comprising:
 a memory cell region having a first metal pad and including a memory cell array,   the memory cell array including a plurality of memory blocks having a plurality of memory cells connected to a plurality of word-lines and a plurality of bit-lines in the memory cell region;   a peripheral circuit region having a second metal pad and being vertically connected to the first metal pad through the second metal pad,
 the peripheral circuit region including a row decoder configured to select one of the plurality of word-lines in the peripheral circuit region, a page buffer circuit having a plurality of page buffers connected to the plurality of bit-lines, and a control logic, 
   the control logic configured to receive a command latch enable (CLE) signal, an address latch enable (ALE) signal, a chip enable (CE) signal, a write enable (WE) signal, a read enable (RE) signal, and a DQS signal through control pins, and to latch a command or an address on an edge of the WE signal according to the CLE signal and the ALE signal, for performing an advanced operation,   wherein the advanced operation includes a program operation, a read operation, or an erase operation according to an advanced operation mode different from a normal operation mode to improve reliability.   
     
     
         2 . The non-volatile memory device of  claim 1 , wherein the advanced operation mode includes a word-line recovery control operation different from the normal operation mode. 
     
     
         3 . The non-volatile memory device of  claim 2 , wherein the word-line recovery control operation includes varying a recovery level according to a wear-out pattern of a memory block among the plurality of memory blocks. 
     
     
         4 . The non-volatile memory device of  claim 2 , wherein the word-line recovery control operation includes varying a recovery time according to a wear-out pattern of the memory block among the plurality of memory blocks. 
     
     
         5 . The non-volatile memory device of  claim 2 , wherein the word-line recovery control operation includes varying a discharge path of a recovery current according to a wear-out pattern of a memory block among the plurality of memory blocks. 
     
     
         6 . A controller, comprising:
 control pins configured to provide a command latch enable (CLE) signal, an address latch enable (ALE) signal, a chip enable (CE) signal, a write enable (WE) signal, a read enable (RE) signal, and a DQS signal to at least one non-volatile memory device;   an error correction circuit configured to receive data of a patrol read operation for a memory block from the at least one non-volatile memory device and to correct an error of the received data; and   at least one processor configured to perform a reclaim on the memory block when a number of errors corrected in the error correction circuit is equal to or greater than a reference value, to determine a wear-out reason for the memory block, to write a wear-out pattern for the wear-out reason in the memory block, to read the wear-out pattern when the memory block is reused, to select an operation mode according to the wear-out pattern, and to perform a program operation, a read operation, or an erase operation for the memory block of the at least one non-volatile memory device according to the selected operation mode.   
     
     
         7 . The controller of  claim 6 , wherein the at least one processor selects, when the memory block is reused, an advanced operation mode different from a normal operation mode to improve reliability. 
     
     
         8 . The controller of  claim 6 , wherein the at least one processor is configured to select the operation mode on a basis of the wear-out pattern and environmental information. 
     
     
         9 . The controller of  claim 6 , further comprising:
 a word-line recovery control table according to the wear-out pattern.   
     
     
         10 . The controller of  claim 9 , wherein the word-line recovery control table includes recovery time information, recovery level information, or recovery discharge path information, corresponding to the wear-out pattern. 
     
     
         11 . A storage device, comprising:
 at least one non-volatile memory device; and   a controller connected to the at least one non-volatile memory device through control pins,   the controller being configured to provide a command latch enable (CLE) signal, an address latch enable (ALE) signal, a chip enable (CE) signal, a write enable (WE) signal, a read enable (RE) signal, and a DQS signal to the at least one non-volatile memory device and configured to read data from the at least one non-volatile memory device,   wherein the at least one non-volatile memory device is configured, by latching a command or an address on an edge of the WE signal according to the CLE signal and the ALE signal, to perform a core operation for improving reliability, and   wherein the controller is configured to check a wear-out pattern of a memory block of the non-volatile memory device to perform the core operation, and to select a word-line recovery mode using the wear-out pattern, and   wherein the at least one non-volatile memory device is configured to perform the core operation according to the selected word-line recovery mode by the controller.   
     
     
         12 . The storage device of  claim 11 , wherein the word-line recovery mode includes:
 selecting a recovery time according to the wear-out pattern;   selecting a recovery level according to the wear-out pattern; or   selecting a recovery discharge path according to the wear-out pattern.   
     
     
         13 . The storage device of  claim 11 , wherein the wear-out pattern is classified into a charge loss pattern and a charge gain pattern. 
     
     
         14 . The storage device of  claim 11 , wherein a level of an erase operation is determined according to the wear-out pattern. 
     
     
         15 . The storage device of  claim 11 , wherein a verification level for verifying a program state varies according to the wear-out pattern. 
     
     
         16 . The storage device of  claim 11 , wherein a bit stored in the memory cell varies according to the wear-out pattern. 
     
     
         17 . The storage device of  claim 11 , wherein the program method varies according to the wear-out pattern. 
     
     
         18 . The storage device of  claim 11 , further comprising:
 writing the wear-out pattern in the memory block.   
     
     
         19 . The storage device of  claim 18 , wherein the wear-out pattern is stored in at least one memory cell or at least one flag cell. 
     
     
         20 . The storage device of  claim 11 , wherein the checking the wear-out pattern includes reading cell count information corresponding to a threshold voltage distribution of memory cells connected to one of word-lines of the memory block.