Method of forming contact structures

Abstract

A method according to the present disclosure includes receiving a workpiece that includes a first gate structure including a first cap layer thereon, a first source/drain contact adjacent the first gate structure, a second gate structure including a second cap layer thereon, a second source/drain contact, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, and a first dielectric layer over the ESL. The method further includes forming a butted contact opening to expose the first cap layer and the first source/drain contact, forming a butted contact in the butted contact opening, after the forming of the butted contact, depositing a second dielectric layer, forming a source/drain contact via opening through the second dielectric layer, the ESL layer, and the first dielectric layer to expose the second source/drain contact, and forming a source/drain contact via in the source/drain contact via opening.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a first gate structure comprising a first cap layer thereon;   a first source/drain contact adjacent the first gate structure;   a second gate structure comprising a second cap layer thereon;   a second source/drain contact;   an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact;   a first dielectric layer over the ESL;   a second dielectric layer over the first dielectric layer;   a butted contact spanning over the first gate structure and the first source/drain contact, the butted contact being in contact with the first source/drain contact and the first cap layer;   a source/drain contact via disposed over the second source/drain contact; and   a gate contact disposed over the second cap layer,   wherein the second dielectric layer is disposed directly on a top surface of the butted contact.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the first source/drain contact and the second source/drain contact comprise cobalt and are free of a barrier layer. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the first cap layer and the second cap layer comprise fluorine-free tungsten. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the butted contact comprises tungsten. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein a top surface of the butted contact and a top surface of the first dielectric layer are coplanar. 
     
     
         6 . The semiconductor structure of  claim 1 , further comprising:
 a dielectric capping layer disposed over the first cap layer.   
     
     
         7 . The semiconductor structure of  claim 6 , further comprising:
 a first gate spacer and a second gate spacer sandwiching the first gate structure, the first cap layer, and the dielectric capping layer.   
     
     
         8 . The semiconductor structure of  claim 7 , wherein the butted contact comprises: 
 an upper portion disposed in the ESL and the first dielectric layer; and   a lower portion extending downward from the upper portion through the dielectric capping layer,   wherein a bottom surface of the upper portion lands on a top surface of the first gate spacer and a top surface of the first source/drain contact,   wherein a bottom surface of the lower portion lands on the first cap layer.   
     
     
         9 . The semiconductor structure of  claim 1 , wherein a portion of the source/drain contact via extends into the second source/drain contact and undercuts the ESL. 
     
     
         10 . A semiconductor structure, comprising:
 a first active region and a second active region aligned lengthwise along a first direction and spaced apart from one another;   a first gate segment extending lengthwise along a second direction perpendicular to the first direction and wrapping over a channel region of the first active region;   a second gate segment extending lengthwise along the second direction and wrapping over a channel region of the second active region;   a first source/drain contact extending lengthwise along the second direction over a source/drain region of the first active region;   a second source/drain contact extending lengthwise along the second direction over a source/drain region of the second active region;   a first butted contact including a first lower portion in contact with the first gate segment and a first upper portion spanning over and contacting the first source/drain contact; and   a second butted contact including a second lower portion in contact with the second gate segment and a second upper portion spanning over and contacting the second source/drain contact.   
     
     
         11 . The semiconductor structure of  claim 10 ,
 wherein the first active region comprises a first fin structure,   wherein the second active region comprises a second fin structure.   
     
     
         12 . The semiconductor structure of  claim 10 ,
 wherein the first active region comprises a first vertical stack of nanostructures,   wherein the second active region comprises a second vertical stack of nanostructures.   
     
     
         13 . The semiconductor structure of  claim 10 , further comprising:
 a third active region extending lengthwise along the first direction;   a third gate segment extending lengthwise along the second direction and wrapping over a first channel region of the third active region;   a fourth gate segment extending lengthwise along the second direction and wrapping over a second channel region of the third active region; and   a third source/drain contact extending lengthwise along the second direction and disposed between the third gate segment and the fourth gate segment,   wherein the third gate segment and the first gate segment are aligned along the second direction,   wherein the fourth gate segment and the second gate segment are aligned along the second direction.   
     
     
         14 . The semiconductor structure of  claim 13 , further comprising:
 an etch stop layer (ESL) disposed over a top surface of the third source/drain contact; and   a source/drain contact via extending through the ESL to contact the third source/drain contact.   
     
     
         15 . The semiconductor structure of  claim 14 , wherein a portion of the source/drain contact via extends into the third source/drain contact and undercuts the ESL. 
     
     
         16 . A structure, comprising:
 an active region extending lengthwise along a first direction and comprising a source/drain region and a channel region adjacent the source/drain region;   a source/drain feature disposed over the source/drain region;   a first gate structure disposed over the channel region;   a metal cap layer over the first gate structure;   a dielectric capping layer over the metal cap layer;   a first gate spacer disposed along and in contact with sidewalls of the first gate structure, the metal cap layer and the dielectric capping layer;   a contact etch stop layer (CESL) disposed along and in contact with the first gate spacer and a top surface of the source/drain feature;   a first interlayer dielectric layer (ILD) over the CESL;   a source/drain contact extending through the first ILD and the CESL to contact the source/drain feature by way of a silicide feature;   an etch stop layer (ESL) disposed over a top surface of the CESL, a top surface of the first ILD layer, and a top surface of the dielectric capping layer;   a second ILD layer over the ESL; and   a local interconnect structure comprising:
 a lower portion extending through the dielectric capping layer to contact the metal cap layer, and 
 an upper portion over the lower portion and a top surface of the source/drain contact, 
   wherein a top surface of the upper portion is coplanar with a top surface of the second ILD layer.   
     
     
         17 . The structure of  claim 16 , wherein the metal cap layer comprises tungsten. 
     
     
         18 . The structure of  claim 16 , wherein the dielectric capping layer comprises silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, or hafnium oxide. 
     
     
         19 . The structure of  claim 16 , wherein the local interconnect structure comprises:
 a barrier layer; and   a metal fill layer over the barrier layer,   wherein the metal fill layer is spaced apart from the second ILD, the ESL, the first gate spacer, and the dielectric capping layer by the barrier layer.   
     
     
         20 . The structure of  claim 19 ,
 wherein the barrier layer comprises titanium nitride,   wherein the metal fill layer comprises tungsten.