Deterministic voltage-controlled magnetic anisotropy (vcma) mram with spin-transfer torque (stt) mram assistance

Abstract

An approach for providing a semiconductor structure for a stacked magnetoresistive random-access memory (MRAM) device that includes a first magnetic tunnel junction on a bottom electrode and at least one second magnetic tunnel junction above the first magnetic tunnel junction. The semiconductor structure includes the first magnetic tunnel junction is a voltage-controlled magnetic anisotropy (VCMA) magnetic tunnel junction of a voltage-controlled magnetic anisotropy (VCMA) MRAM device. The VCMA-MRAM device is composed of a first reference layer, a first tunnel barrier layer, and a first free layer. The semiconductor structure includes the second magnetic tunnel junction that is a spin-transfer torque (STT) magnetic tunnel junction of a STT-MRAM device. The STT-MRAM device is composed of a second reference layer, a second tunnel barrier layer, and a second free layer where the STT magnetic tunnel junction has a smaller cross-sectional area than the VCMA magnetic tunnel junction (MTJ).

What is claimed is: 
     
         1 . A semiconductor structure of a stacked magnetoresistive random-access memory (MRAM) device, the semiconductor structure comprising:
 a first magnetic tunnel junction on a bottom electrode; and   at least one second magnetic tunnel junction above the first magnetic tunnel junction.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the first magnetic tunnel junction is a voltage-controlled magnetic anisotropy (VCMA) magnetic tunnel junction of a VCMA-MRAM device that is composed of a first reference layer, a first tunnel barrier layer, and a first free layer. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein the at least one second magnetic tunnel junction is a spin-transfer torque (STT) magnetic tunnel junction of an STT-MRAM device that is composed of a second reference layer, a second tunnel barrier layer, and a second free layer. 
     
     
         4 . The semiconductor structure of  claim 3 , wherein the first magnetic tunnel junction has a larger cross-sectional area than the at least one second magnetic tunnel junction than. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein a stray field generated by the magnetization of the second free layer of the at least second magnetic tunnel junction aligns a magnetization of the first free layer of the VCMA-MRAM device with the second free layer of the STT-MRAM. 
     
     
         6 . The semiconductor structure of  claim 4 , wherein an etch stop layer is over the first free layer of the VCMA-MRAM device. 
     
     
         7 . The semiconductor structure of  claim 4 , wherein the at least one second magnetic tunnel junction of the STT-MRAM is surrounded by a sidewall spacer. 
     
     
         8 . The semiconductor structure of  claim 7 , wherein a dielectric material encapsulates vertical sides of the sidewall spacer around the at least one second magnetic tunnel junction of the STT-MRAM and the first magnetic tunnel junction of the VCMA-MRAM. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein the first magnetic tunnel junction is a spin-transfer torque (STT) magnetic tunnel junction of an STT-MRAM and the at least one second magnetic tunnel junction is a voltage-controlled magnetic (VCMA) tunnel junction of a VCMA-MRAM. 
     
     
         10 . The semiconductor structure of  claim 9 , wherein the STT magnetic tunnel junction of the STT-MRAM has a smaller cross-sectional area than the at least one second magnetic tunnel junction of the VCMA tunnel junction of the VCMA-MRAM. 
     
     
         11 . The semiconductor structure of  claim 3 , wherein the VCMA magnetic tunnel junction and the STT magnetic tunnel junction have a same cross-sectional area. 
     
     
         12 . The semiconductor structure of  claim 11 , wherein a second STT magnetic tunnel junction of the STT-MRAM device is tuned to ensure that a Resistance-Area product of the second tunnel barrier layer of the STT magnetic tunnel junction is less than the Resistance-Area product of the first VCMA magnetic tunnel junction of the VCMA-MRAM. 
     
     
         13 . The semiconductor structure of  claim 1 , further comprising:
 a hardmask over the at least one magnetic tunnel junction; and   a top electrode over the hardmask.   
     
     
         14 . The semiconductor structure of  claim 1 , wherein a width of a hardmask on the at least one second magnetic tunnel junction determines a width of the at least one magnetic tunnel junction. 
     
     
         15 . A method of performing a write operation on a stacked magnetoresistive random-access memory (MRAM) device, the method comprising:
 applying a single, high voltage pulse to a stacked MRAM, wherein the stacked MRAM device is composed of a bottom voltage-controlled magnetic anisotropy (VCMA) MRAM device and a top spin-transfer torque (STT) MRAM device with a smaller width than the VCMA-MRAM device.   
     
     
         16 . The method of  claim 15 , wherein the single, high voltage pulse switches the top STT-MRAM and a stray field of the top STT-MRAM switches the bottom VCMA-MRAM to match a magnetization of the top STT-MRAM. 
     
     
         17 . A method of performing a write operation on a stacked magnetoresistive random-access memory (MRAM) device, the method comprising:
 applying a small current to switch a top spin-transfer torque (STT) MRAM device that is over a bottom voltage-controlled magnetic anisotropy (VCMA) MRAM device to switch the top STT-MRAM device; and   applying a voltage across a top electrode and a bottom electrode.   
     
     
         18 . The method of  claim 17 , wherein the voltage lowers an energy barrier of the VCMA-MRAM device. 
     
     
         19 . The method of  claim 18 , wherein a stray field of the top STT-MRAM device switches the VCMA-MRAM device. 
     
     
         20 . The method of  claim 19 , wherein a first free layer of the VCMA-MRAM device has a same direction as a second free layer of the STT VCMA device.