Structure for microelectromechanical systems (mems) devices to control pressure at high temperature

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a microelectromechanical systems (MEMS) structure overlying a substrate. A capping structure overlies the MEMS structure. The capping structure at least partially defines a cavity. The MEMS structure is disposed in the cavity. An outgas structure adjacent to the cavity. The outgas structure comprises an amorphous material.

What is claimed is: 
     
         1 . An integrated chip, comprising:
 a microelectromechanical systems (MEMS) structure overlying a substrate;   a capping structure over the MEMS structure, wherein the capping structure at least partially defines a cavity, wherein the MEMS structure is disposed in the cavity; and   an outgas structure adjacent to the cavity, wherein the outgas structure comprises an amorphous material.   
     
     
         2 . The integrated chip of  claim 1 , further comprising:
 a bumper structure underlying the MEMS structure, wherein an upper surface of the outgas structure is vertically offset an upper surface of the bumper structure in a direction towards the substrate.   
     
     
         3 . The integrated chip of  claim 1 , wherein a height of the outgas structure continuously decreases from a middle region of the outgas structure towards an outer sidewall of the outgas structure. 
     
     
         4 . The integrated chip of  claim 1 , wherein outer sidewalls of the outgas structure are slanted. 
     
     
         5 . The integrated chip of  claim 1 , further comprising:
 a plurality of conductive bond structures disposed between the capping structure and the substrate, wherein a lower surface of the outgas structure is disposed above a lower surface of the conductive bond structures.   
     
     
         6 . The integrated chip of  claim 5 , further comprising:
 a getter layer disposed between the capping structure and the substrate, wherein a lower surface of the getter layer is aligned with the lower surface of the conductive bond structures.   
     
     
         7 . The integrated chip of  claim 6 , wherein the plurality of conductive bond structures comprises a first conductive bond structure disposed laterally between the getter layer and the outgas structure, wherein the getter layer is disposed in the cavity. 
     
     
         8 . The integrated chip of  claim 1 , further comprising:
 an interconnect structure disposed between the substrate and the capping structure, wherein the interconnect structure comprises an upper conductive wire layer disposed between the substrate and the outgas structure, wherein a getter layer is disposed along an upper surface of the upper conductive wire layer.   
     
     
         9 . An integrated chip, comprising:
 a dielectric structure overlying a first substrate;   a second substrate overlying the dielectric structure, wherein the second substrate and the dielectric structure at least partially define a first cavity;   a first microelectromechanical systems (MEMS) structure disposed within the first cavity;   an outgas structure disposed in the dielectric structure and having a surface abutting the first cavity; and   a first getter layer disposed within the first cavity.   
     
     
         10 . The integrated chip of  claim 9 , wherein an area of the surface of the outgas structure is greater than an area of a surface of the first getter layer abutting the first cavity. 
     
     
         11 . The integrated chip of  claim 9 , wherein a top surface of the first getter layer is disposed below a bottom surface of the outgas structure. 
     
     
         12 . The integrated chip of  claim 9 , further comprising:
 a second MEMS structure disposed within a second cavity laterally adjacent to the first cavity; and   a second getter layer disposed within the second cavity and underlying the second MEMS structure, wherein an area of one or more surfaces of the second getter layer abutting the second cavity is greater than an area of one or more surfaces of the first getter layer abutting the first cavity.   
     
     
         13 . The integrated chip of  claim 9 , further comprising:
 a bumper structure directly overlying the first getter layer.   
     
     
         14 . The integrated chip of  claim 9 , wherein the outgas structure comprises hydrogenated amorphous silicon. 
     
     
         15 . The integrated chip of  claim 9 , wherein the outgas structure has an outgas depletion temperature that is greater than 420 degrees Celsius. 
     
     
         16 . A method for manufacturing an integrated chip, the method comprising:
 forming a dielectric structure over a first substrate;   forming an outgas structure in the dielectric structure, wherein the outgas structure has an outgas depletion temperature;   etching a second substrate to define a first movable element in the second substrate; and   performing a bonding process to bond the second substrate to the first substrate, wherein the first movable element overlies the outgas structure, and wherein the bonding process reaches a maximum bonding temperature less than the outgas depletion temperature.   
     
     
         17 . The method of  claim 16 , wherein the bonding process comprises performing a eutectic bonding process. 
     
     
         18 . The method of  claim 16 , further comprising:
 forming a dielectric capping layer over the dielectric structure and the outgas structure;   forming a bumper structure within the dielectric structure laterally adjacent to the outgas structure; and   performing a removal process to remove the dielectric capping layer from over an upper surface of the outgas structure after forming the bumper structure.   
     
     
         19 . The method of  claim 16 , further comprising:
 performing another bonding process to bond a third substrate to the second substrate, wherein the another bonding process is different from the bonding process.   
     
     
         20 . The method of  claim 16 , wherein forming the outgas structure comprises:
 etching the dielectric structure to form an opening in the dielectric structure; and   depositing the outgas structure in the opening by plasma-enhanced chemical vapor deposition (PECVD) using a precursor gas comprising silane.