Pixel having an organic light emitting diode and method of fabricating the pixel

Abstract

A pixel having an organic light emitting diode (OLED) and method for fabricating the pixel is provided. A planarization dielectric layer is provided between a thin-film transistor (TFT) based backplane and OLED layers. A through via between the TFT backplane and the OLED layers forms a sidewall angle of less than 90 degrees to the TFT backplane. The via area and edges of an OLED bottom electrode pattern may be covered with a dielectric cap.

What is claimed is: 
     
         1 - 20 . (canceled) 
     
     
         21 . A pixel comprising:
 a first electrode;   a second electrode;   one or more organic light emitting diode (OLED) layers between the first and second electrodes; and   an insulating material layer deposited between the first electrode and the one or more OLED layers covering all the edges of said first electrode while leaving at least one portion of the first electrode in direct contact with the one or more OLED layers.   
     
     
         22 . The pixel as claimed in  claim 21 , wherein said insulating material layer is patterned such that it insulates the one or more OLED layers from the first electrode at all edges of the first electrode. 
     
     
         23 . The pixel as claimed in  claim 22 , wherein said insulating material layer includes polymer dielectric or inorganic insulator. 
     
     
         24 . The pixel as claimed in  claim 22 , wherein a material of said insulating material layer includes at least one of benzocylobutene (BCB), polyimide, polymer dielectric, silicon nitride, and a thin film inorganic. 
     
     
         25 . The pixel as claimed in  claim 21 , wherein said insulating material layer is patterned to avoid breakage of the second electrode. 
     
     
         26 . The pixel as claimed in  claim 21 , wherein said insulating material layer is patterned to avoid breakage of the one or more OLED layers. 
     
     
         27 . The pixel as claimed in  claim 26 , wherein said insulating material layer includes polymer dielectric or inorganic insulator. 
     
     
         28 . The pixel as claimed in  claim 26 , wherein a material of said insulating material layer includes at least one of BCB, polyimide, polymer dielectric, silicon nitride, and a thin film inorganic. 
     
     
         29 . The pixel as claimed in  claim 21 , further comprising:
 a backplane for electrically driving the one or more OLED layers;   a planarization dielectric layer provided between the backplane and the first electrode; and   a shield electrode formed over a thin-film transistor (TFT) formed within the backplane.   
     
     
         30 . The pixel as claimed in  claim 21 , further comprising:
 a backplane for electrically driving the one or more OLED layers;   a planarization dielectric layer provided between the backplane and the first electrode so as to planarize the vertical profile on the backplane, said planarization dielectric layer being in direct contact with both said backplane and said first electrode, a via in said planarization dielectric layer for providing a communication path between said backplane and said first electrode,   wherein the sidewall of said via in the planarization layer is sloped against the backplane, wherein said first electrode is directly on top of said planarized dielectric layer and extends through said via into direct contact with said backplane and wherein said insulating material layer covers said via.   
     
     
         31 . The pixel as claimed in  claim 30 , wherein said insulating material layer is patterned such that it insulates the one or more OLED layers from the first electrode at all edges of the first electrode and in and around the via, while leaving the rest of the first electrode in direct contact with the one or more OLED layers. 
     
     
         32 . The pixel as claimed in  claim 30 , further comprising continuous sidewall coverage by pixel electrode material in the via profile in the planarization dielectric layer. 
     
     
         33 . The pixel as claimed in  claim 30 , wherein the planarization dielectric layer includes photosensitive BCB, the slope of the via being adjusted by the exposure time of the photosensitive BCB. 
     
     
         34 . The pixel as claimed in  claim 21 , further comprising: a backplane for electrically driving the one or more OLED layers; 
 wherein the backplane comprises a thin-film transistor (TFT) based backplane, the TFT based backplane being vertically integrated with the one or more OLED layers and located below said first electrode to form a top-emitting OLED, the TFT based backplane comprising source and drain nodes, and further includes: 
 a substrate; 
 an interlayer dielectric layer on the source and drain nodes; and 
 an interconnection plate patterned on a via of the interlayer dielectric layer and being connected to the source or drain node, for said driving the one or more OLED layers. 
   
     
     
         35 . A method of fabricating a pixel, the pixel having a first electrode, a second electrode, one or more OLED layers between the first and second electrodes, the method comprising the steps of:
 depositing said first electrode;   depositing an insulating material layer covering all the edges of said first electrode while leaving at least one portion of the first electrode for direct contact with the one or more OLED layers; and   depositing said one or more OLED layers over said first electrode and said insulating material layer.   
     
     
         36 . A method as claimed in  claim 35 , wherein the pixel includes a substrate and a backplane for electrically driving the one or more OLED layers the method further comprising: 
 providing the backplane on said substrate;   providing a dielectric layer on the backplane, including the step of planarizing a vertical profile in the dielectric layer so as to planarize the vertical profile on the substrate with the backplane, said planarized dielectric layer being in direct contact with said backplane; and   forming a via in said planarization dielectric layer to provide a communication path between said backplane and said first electrode, such that the sidewall of the via in the planarization layer is sloped against the backplane,   wherein depositing said first electrode above said backplane includes depositing said first electrode directly on top of said planarized dielectric layer and extending through said via into direct contact with said backplane and wherein said depositing the insulating material layer on said first electrode comprises patterning the insulating material layer in such a way that it covers the via.   
     
     
         37 . A method as claimed in  claim 35 , wherein said depositing said insulating material layer comprises patterning the insulating material layer in such a way that it insulates the one or more OLED layers from the first electrode at all edges of the first electrode. 
     
     
         38 . A method as claimed in  claim 35 , wherein depositing said insulating material layer comprises patterning the insulating material layer in such a way that it avoids breakage of the one or more OLED layers. 
     
     
         39 . A method as claimed in  claim 36 , wherein said depositing said insulating material layer comprises patterning the insulating material layer in such a way that it insulates the one or more OLED layers from the first electrode at all edges of the first electrode and in and around the via while leaving the rest of the first electrode in direct contact with the one or more OLED layers. 
     
     
         40 . A method as claimed in  claim 36 , wherein the planarization dielectric layer is provided including photosensitive benzocylobutene (BCB), further comprising the step of adjusting the exposure time of the photosensitive BCB such that the sidewall of the via in the planarization layer is sloped against the backplane. 
     
     
         41 . A method as claimed in  claim 36 , further comprising the step of providing continuous sidewall coverage by pixel electrode material in the via profile in the planarization dielectric layer.