Amplifier Gain-Tuning Circuits and Methods

Abstract

Circuits and methods for improving the noise figure (NF) of an amplifier, particularly an LNA, in high-gain modes while improving the IIP3 of the amplifier in low-gain modes. The source of an amplifier common-source FET is coupled to circuit ground thorough a degeneration circuit comprising a two-port inductor and a bypass switch coupled in parallel with the inductor. A switched feedback circuit is coupled between the gate of the common-source FET and a feedback node in the amplifier output signal path. During a low gain mode, the inductor is entirely bypassed and the enabled feedback circuit lowers the input impedance of the common-source FET and reduces the gain of the amplifier circuit, essentially eliminating the need for a degeneration inductor. During a high gain mode, the source of the common-source FET is coupled to circuit ground through the inductor and the feedback circuit is disabled. Other gain modes are supported.

What is claimed is: 
     
         1 . An amplifier including:
 (a) an amplifier core including:
 (1) at least two FETs coupled in a stacked arrangement; 
 (2) an input terminal configured to receive a radio-frequency (RF) signal and coupled to a first FET of the at least two FETs; 
 (3) a degeneration terminal coupled to the first FET of the at least two FETs; 
 (4) an amplified-signal terminal coupled to a second FET of the at least two FETs; and 
 (5) a feedback node in an output signal path of the amplifier core and coupled to at least one FET of the at least two FETs; 
   (b) a degeneration circuit coupled between the degeneration terminal and circuit ground, the generation circuit including:
 (1) a degeneration inductance; and 
 (2) a bypass switch coupled in parallel with the degeneration inductance; and 
   (c) a feedback circuit coupled between the input terminal and the feedback node through a feedback switch, the feedback circuit being selectively enabled by closing the feedback switch, and selectively disabled by opening the feedback switch;
 wherein in a first low gain mode of operation, the feedback circuit is enabled and the bypass switch is in a closed state, bypassing the degeneration inductance, thereby removing the degeneration inductance from between the degeneration terminal and circuit ground; and 
 wherein in a first high gain mode of operation, the feedback circuit is disabled and the bypass switch is in an open state, thereby coupling the degeneration terminal to circuit ground through the degeneration inductance; 
 wherein in a low-gain mode of operation different from the first low gain mode of operation, the feedback circuit is enabled and the bypass switch is in an open state; and 
 wherein in a high-gain mode of operation different from the first high gain mode of operation, the feedback circuit is enabled and the bypass switch is in an open state. 
   
     
     
         2 . The invention of  claim 1 , wherein the amplifier is a low-noise amplifier. 
     
     
         3 . The invention of  claim 1 , wherein the feedback circuit includes a resistor, a capacitor, and the feedback switch coupled in series. 
     
     
         4 . The invention of  claim 1 , wherein the degeneration inductance is a two-port coiled integrated circuit inductor. 
     
     
         5 . The invention of  claim 1 , further including an impedance matching circuit coupled to the input terminal and configured to receive the RF signal. 
     
     
         6 . The invention of  claim 1 , further including a load matching and bias feed circuit coupled to the amplified-signal terminal. 
     
     
         7 . The invention of  claim 1 , further including a bias circuit coupled to the amplifier core. 
     
     
         8 . The invention of  claim 1 , wherein the amplifier is implemented as an integrated circuit fabricated in a silicon-on-insulator technology and includes MOS devices. 
     
     
         9 . The invention of  claim 1 , wherein the amplifier is implemented as an integrated circuit comprising part of a communications receiver or transmitter or transceiver. 
     
     
         10 . A method of gain-tuning an amplifier that includes an amplifier core including an input terminal configured to receive a radio-frequency (RF) signal, a degeneration terminal, and a feedback node in an amplifier output signal path, the method including:
 (a) in a first low gain mode of operation, enabling feedback between the input terminal and the feedback node in the amplifier output signal path and bypassing a degeneration inductance with respect to a signal path from the degeneration terminal to circuit ground; and   (b) in a first high gain mode of operation, disabling feedback between the input terminal and the feedback node in the amplifier output signal path and coupling the degeneration inductance between the degeneration terminal and circuit ground.   
     
     
         11 . The method of  claim 10 , wherein in a low-gain mode of operation different from the first low gain mode of operation, enabling feedback between the input terminal and the feedback node in the amplifier output signal path and coupling the degeneration inductance between the degeneration terminal and circuit ground. 
     
     
         12 . The method of  claim 10 , wherein in a high-gain mode of operation different from the first high gain mode of operation, enabling feedback between the input terminal and the feedback node in the amplifier output signal path and coupling the degeneration inductance between the degeneration terminal and circuit ground. 
     
     
         13 . The method of  claim 10 , wherein the feedback is from a feedback circuit that includes a resistor, a capacitor, and a switch coupled in series. 
     
     
         14 . The method of  claim 10 , wherein the degeneration inductance is a two-port coiled integrated circuit inductor. 
     
     
         15 . The method of  claim 10 , wherein the amplifier further includes an impedance matching circuit coupled to the input terminal and configured to receive the RF signal. 
     
     
         16 . The method of  claim 10 , wherein the amplifier further includes a load matching and bias feed circuit coupled to the amplified-signal terminal. 
     
     
         17 . The method of  claim 10 , wherein the amplifier further includes a bias circuit coupled to the amplifier core. 
     
     
         18 . The method of  claim 10 , wherein the amplifier is implemented as an integrated circuit fabricated in a silicon-on-insulator technology and includes MOS devices. 
     
     
         19 . A method of gain-tuning an amplifier that includes an amplifier core including an input terminal configured to receive a radio-frequency (RF) signal, a degeneration terminal, and a feedback node in an amplifier output signal path, the method including:
 (a) in a first low gain mode of operation, enabling feedback between the input terminal and the feedback node in the amplifier output signal path and bypassing a degeneration inductance with respect to a signal path from the degeneration terminal to circuit ground;   (b) in a first high gain mode of operation, disabling feedback between the input terminal and the feedback node in the amplifier output signal path and coupling the degeneration inductance between the degeneration terminal and circuit ground;   (c) in a low-gain mode of operation different from the first low gain mode of operation, enabling feedback between the input terminal and the feedback node in the amplifier output signal path and coupling the degeneration inductance between the degeneration terminal and circuit ground; and   (d) in a high-gain mode of operation different from the first high gain mode of operation, enabling feedback between the input terminal and the feedback node in the amplifier output signal path and coupling the degeneration inductance between the degeneration terminal and circuit ground.   
     
     
         20 . The invention of  claim 19 , wherein the amplifier is a low-noise amplifier.