Display device

Abstract

A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

What is claimed is: 
     
         1 .  A semiconductor device comprising:
 a plurality of scan line driver circuits over a substrate;   a pixel portion over the substrate, the pixel portion being provided between the plurality of scan line driver circuits;   a protective circuit over the substrate, the protective circuit being provided outside of the pixel portion;   a scan line electrically connected to one of the plurality of scan line driver circuits and the protective circuit; and   a common wiring electrically connected to the protective circuit,   wherein the protective circuit comprises a first transistor and a second transistor,   wherein the scan line and a first conductive layer are provided over the substrate,   wherein the scan line comprises a first region extending in a first direction and a second region extending in a second direction different from the first direction,   wherein the second region of the scan line is configured to function as a first gate electrode of the first transistor,   wherein a first insulating layer is provided over the scan line and the first conductive layer,   wherein the scan line is electrically connected to a second conductive layer provided over the first insulating layer,   wherein the second conductive layer comprises a first region configured to function as one of a source electrode and a drain electrode of the first transistor and a second region configured to function as one of a source electrode and a drain electrode of the second transistor,   wherein the first conductive layer is configured to function as a second gate electrode of the second transistor,   wherein the common wiring is provided over the first insulating layer,   wherein the common wiring comprises a first region configured to function as the other of the source electrode and the drain electrode of the first transistor and a second region configured to function as the other of the source electrode and the drain electrode of the second transistor, and   wherein the common wiring is electrically connected to the first conductive layer.   
     
     
         2 . A semiconductor device comprising:
 a plurality of scan line driver circuits over a substrate;   a pixel portion over the substrate, the pixel portion being provided between the plurality of scan line driver circuits;   a protective circuit over the substrate, the protective circuit being provided outside of the pixel portion;   a scan line electrically connected to one of the plurality of scan line driver circuits and the protective circuit; and   a common wiring electrically connected to the protective circuit,   wherein the protective circuit comprises a first transistor and a second transistor,   wherein the scan line and a first conductive layer are provided over the substrate,   wherein the scan line comprises a first region extending in a first direction and a second region extending in a second direction different from the first direction,   wherein the second region of the scan line is configured to function as a first gate electrode of the first transistor,   wherein a first insulating layer is provided over the scan line and the first conductive layer,   wherein the scan line is electrically connected to a second conductive layer provided over the first insulating layer,   wherein the second conductive layer comprises a first region configured to function as one of a source electrode and a drain electrode of the first transistor and a second region configured to function as one of a source electrode and a drain electrode of the second transistor,   wherein the first conductive layer is configured to function as a second gate electrode of the second transistor,   wherein the common wiring is provided over the first insulating layer,   wherein the common wiring comprises a first region configured to function as the other of the source electrode and the drain electrode of the first transistor and a second region configured to function as the other of the source electrode and the drain electrode of the second transistor,   wherein the common wiring is electrically connected to the first conductive layer, and   wherein the first conductive layer extends in the second direction.   
     
     
         3 . A semiconductor device comprising:
 a plurality of scan line driver circuits over a substrate;   a pixel portion over the substrate, the pixel portion being provided between the plurality of scan line driver circuits;   a protective circuit over the substrate, the protective circuit being provided outside of the pixel portion;   a scan line electrically connected to one of the plurality of scan line driver circuits and the protective circuit; and   a common wiring electrically connected to the protective circuit,   wherein the protective circuit comprises a first transistor and a second transistor,   wherein the scan line and a first conductive layer are provided over the substrate,   wherein the scan line comprises a first region extending in a first direction and a second region extending in a second direction different from the first direction,   wherein the second region of the scan line is configured to function as a first gate electrode of the first transistor,   wherein a first insulating layer is provided over the scan line and the first conductive layer,   wherein the scan line is electrically connected to a second conductive layer provided over the first insulating layer,   wherein the second conductive layer comprises a first region configured to function as one of a source electrode and a drain electrode of the first transistor and a second region configured to function as one of a source electrode and a drain electrode of the second transistor,   wherein the first conductive layer is configured to function as a second gate electrode of the second transistor,   wherein the common wiring is provided over the first insulating layer,   wherein the common wiring comprises a first region configured to function as the other of the source electrode and the drain electrode of the first transistor and a second region configured to function as the other of the source electrode and the drain electrode of the second transistor,   wherein the common wiring is electrically connected to the first conductive layer,   wherein the first conductive layer extends in the second direction,   wherein, in a top view, the first region of the second conductive layer faces the first region of the common wiring, and   wherein, in the top view, the second region of the second conductive layer faces the second region of the common wiring.