Electroluminescent display panel having the emission driving circuit

Abstract

According to one exemplary embodiment of the present disclosure, the electroluminescent display panel may include a plurality of pixels arranged along a row direction and a column direction, an emission line transmitting an emission signal to the plurality of pixels arranged along the row direction and an emission driving circuit providing an emission signal to the plurality of pixels. The emission driving circuit includes a plurality of emission stages wherein the number of emission stages is more than the number of the plurality of pixels arranged along the column direction. Therefore, the pulse width resolution of the display panel may be enhanced and the low gradation stain may be reduced.

1 . An electroluminescent display panel, comprising:
 a plurality of pixels arranged along a row direction and a column direction in a display region, each of the plurality of pixels including a plurality of sub-pixels including a first sub-pixel of a first color, a second sub-pixel of a second color and a third sub-pixel of a third color, each of the plurality of sub-pixels including a light emitting element and a pixel driving circuit for driving the light emitting element, the pixel driving circuit including a driving transistor and an emission transistor;   an emission driving circuit and a gate driving circuit respectively connected to a same pixel row on both sides of the display region;   a plurality of gate lines disposed between respective pixel rows; and   a plurality of emission lines disposed in a direction parallel to the plurality of gate lines;   wherein an emission clock signal is provided to the emission driving circuit; and   wherein an emission signal is output by the emission driving circuit based on the emission clock signal.   
     
     
         2 . The electroluminescent display panel of  claim 1 , wherein the output of the emission signal is synchronized with the emission clock signal. 
     
     
         3 . The electroluminescent display panel of  claim 1 , wherein the output of the emission signal is output with a variable duty ratio. 
     
     
         4 . The electroluminescent display panel of  claim 1 , wherein the emission clock signal includes a first emission clock signal and a second emission clock signal input to each of a plurality of emission stages. 
     
     
         5 . The electroluminescent display panel of  claim 1 , wherein at least two adjacent sub-pixels among the first, second and third sub-pixels in the pixel row or a pixel column have different colors. 
     
     
         6 . The electroluminescent display panel of  claim 1 , wherein at least two adjacent sub-pixels among the first, second and third sub-pixels in the pixel row or a pixel column have the same color as each other. 
     
     
         7 . The electroluminescent display panel of  claim 1 , wherein the emission driving circuit provides the emission signal to the plurality of pixels and includes a plurality of emission stages. 
     
     
         8 . The electroluminescent display panel of  claim 7 ,
 wherein three emission stages among the plurality of emission stages are connected with one pixel row, and   wherein the three emission stages provide the emission signal to the one pixel row through one emission line.   
     
     
         9 . The electroluminescent display panel of  claim 7 ,
 wherein three sub-pixels among the plurality of emission stages are connected to three emission stages respectively,   wherein a first emission clock signal and a second emission clock signal are inputted to each of the plurality of emission stages, and   wherein all the emission stages included in the emission driving circuit provide the emission signal to the sub-pixel rows.   
     
     
         10 . The electroluminescent display panel of  claim 7 , wherein the plurality of emission stages are connected to the plurality of emission lines, and each of the plurality of emission lines is connected to the plurality of pixels emitting different colors. 
     
     
         11 . The electroluminescent display panel of  claim 10 , wherein an output signal from each of the plurality of emission stages is provided as an input signal to one of the plurality of emission stages that is disposed at a next row of the each of the plurality of emission stages outputting the output signal. 
     
     
         12 . The electroluminescent display panel of  claim 10 ,
 wherein the emission signal includes a gate on pulse which turns on an emission transistor, and   a pulse width for the gate on pulse in the emission signal is less than a pulse width of the emission signal provided to the plurality of pixels when a number of the plurality of emission stages and a number of the plurality of pixels arranged along the column direction are the same.   
     
     
         13 . The electroluminescent display panel of  claim 1 ,
 wherein the emission transistor, in operation, controls the driving current to the light emitting diode and is controlled based on the emission signal that occurs based on the emission clock signal from the controller and includes a gate on pulse and a gate off pulse which are repeated at least once in one vertical period, and   wherein a cycle for the emission clock signal is smaller than (one frame period - a blank period of a vertical period)/a number of pixels included in a pixel column.   
     
     
         14 . The electroluminescent display panel of  claim 1 , wherein each of the plurality of emission lines further comprises:
 a second emission line that, in operation, transmits a second emission signal to the second sub-pixels of a first row of pixels of the plurality of pixels that are arranged along the row direction; and   a third emission line that, in operation, transmits a third emission signal to the third sub-pixels of the first row of pixels of the plurality of pixels that are arranged along the row direction, wherein a first set of emission stages is connected to the second and third emission lines.   
     
     
         15 . The electroluminescent display panel of  claim 1 ,
 wherein the emission signal is synchronized with the emission clock signal to determine a pulse width of the emission signal, and   wherein a minimum pulse width of the emission signal is determined based on a cycle of the emission clock signal.   
     
     
         16 . The electroluminescent display panel of  claim 7 , wherein the plurality of emission stages are operated in a pulse width modulation driving method to turn off the emission transistor periodically. 
     
     
         17 . The electroluminescent display panel of  claim 16 , wherein a first set of emission stages includes:
 a first emission stage connected to a first emission line;   a second emission stage connected to a second emission line; and   a third emission stage connected to a third emission line.   
     
     
         18 . The electroluminescent display panel of  claim 16 , wherein a first set of emission stages includes:
 a first emission stage connected to a first emission line, a second emission line and a third emission line; and   a second emission stage connected to the first emission stage.   
     
     
         19 . The electroluminescent display panel of  claim 1 , wherein the gate driving circuit is closer than the emission driving circuit to the display region. 
     
     
         20 . The electroluminescent display panel of  claim 1 , wherein the gate driving circuit is disposed farther from the display region than the emission driving circuit. 
     
     
         21 . The electroluminescent display panel of  claim 1 , wherein a number of gate driving circuits is equal to a number of emission driving circuits. 
     
     
         22 . The electroluminescent display panel of  claim 1 , wherein the gate driving circuit and the emission driving circuit each have a symmetrical structure with respect to the display region. 
     
     
         23 . The electroluminescent display panel of  claim 7 , wherein at least one emission stage among the plurality of emission stages supplies the emission signal to a pixel row in which the third sub-pixel is disposed. 
     
     
         24 . The electroluminescent display panel of  claim 1 , wherein an emission line of the plurality of emission lines is disposed to overlap with at least one of the first, second and third sub-pixels. 
     
     
         25 . The electroluminescent display panel of  claim 1 , wherein an emission line of the plurality of emission lines is connected to a sub-pixel row including any one of the plurality of sub-pixels. 
     
     
         26 . The electroluminescent display panel of  claim 1 , wherein the plurality of sub-pixels are formed to have different areas from each other according to emission colors thereof. 
     
     
         27 . The electroluminescent display panel of  claim 1 , wherein the plurality of sub-pixels are arranged in a zigzag manner in the display region. 
     
     
         28 . The electroluminescent display panel of  claim 1 , wherein the first sub-pixel, the second sub-pixel and the third sub-pixel included in one of the plurality of pixels are disposed along a pixel column. 
     
     
         29 . The electroluminescent display panel of  claim 28 , further comprising a first emission stage connected to the first sub-pixel, a second emission stage connected to the second sub-pixel and a third emission stage connected to the third sub-pixel. 
     
     
         30 . The electroluminescent display panel of  claim 29 , wherein
 the first emission stage outputs a first emission signal and provides the first emission signal to one sub-pixel row emitting red light through a first emission line;   the second emission stage outputs a second emission signal and provides the second emission signal to one sub-pixel row emitting green light through a second emission line; and   the third emission stage outputs a third emission signal and provides the third emission signal to one sub-pixel row emitting blue light through a third emission line.   
     
     
         31 . An electroluminescent display panel comprising:
 a plurality of pixels arranged along a row direction and a column direction in a display region, each of the plurality of pixels including a plurality of sub-pixels including a first sub-pixel of a first color, a second sub-pixel of a second color and a third sub-pixel of a third color, each of the plurality of sub-pixels including a light emitting element and a pixel driving circuit for driving the light emitting element, the pixel driving circuit including a driving transistor and an emission transistor;   an emission driving circuit and a gate driving circuit respectively connected to a same pixel row on both sides of the display region;   a plurality of gate lines disposed between respective pixel rows; and   a plurality of emission lines disposed in a direction parallel to the plurality of gate lines;   wherein an emission clock signal is provided to the emission driving circuit;   wherein an emission signal is output by the emission driving circuit based on the emission clock signal;   wherein each of the plurality of pixels includes the plurality of sub-pixels arranged along a column direction; and   wherein one of the plurality of emission lines is connected to a sub-pixel row including any one of the plurality of sub-pixels.   
     
     
         32 . The electroluminescent display panel of  claim 31 , wherein one of the plurality of emission lines is connected to all of a plurality of sub-pixel rows including each of the plurality of sub-pixels. 
     
     
         33 . The electroluminescent display panel of  claim 31 , wherein a plurality of signal lines for supplying a driving signal to the pixel driving circuit are disposed in each of the plurality of sub-pixels. 
     
     
         34 . The electroluminescent display panel of  claim 33 , wherein the plurality of signal lines include:
 a first driving voltage supply line to which a first driving voltage is supplied;   a second driving voltage supply line to which a second driving voltage is supplied;   a data line supplied with data voltage;   a gate line to which a gate signal is supplied; and   a sensing signal line to which an initialization voltage or a sensing voltage is supplied.   
     
     
         35 . The electroluminescent display panel of  claim 34 , wherein the emission signal for turning on the emission transistor is supplied from the emission driving circuit to one of the plurality of emission lines, and a sensing control signal for turning on a sensing transistor is supplied from the gate driving circuit to the sensing signal line. 
     
     
         36 . The electroluminescent display panel of  claim 31 , wherein the emission transistor is a PMOS type and transistors of the emission driving circuit are the PMOS type. 
     
     
         37 . The electroluminescent display panel of  claim 31 , wherein the plurality of pixels connected to each of the plurality of emission lines emit the same color. 
     
     
         38 . The electroluminescent display panel of  claim 31 , wherein the emission driving circuit includes:
 a first transistor transferring an emission start signal to a Q node;   a second transistor transferring the first emission clock signal to a gate electrode of a sixth transistor;   a third transistor to which a high potential voltage is applied to a first electrode and a first capacitor connected to a second electrode;   the sixth transistor of pull-up type outputting a low potential voltage to one of the plurality of emission lines;   a seventh transistor of pull-down type outputting the high potential voltage to the one of the plurality of emission lines;   an eighth transistor to which a first clock signal is applied through a first electrode thereof and a second capacitor connected between a gate electrode and a second electrode thereof;   a ninth transistor connected between one end of the second capacitor and one end of a third capacitor; and   a tenth transistor having one end to which the high potential voltage is applied and another end connected to a gate electrode of the seventh transistor.   
     
     
         39 . The electroluminescent display panel of  claim 38 , wherein
 the first capacitor has one end connected to the second transistor and another end connected to the third transistor, the Q node, and the gate electrode of the sixth transistor, the first emission clock signal is applied to the one end of the first capacitor through the second transistor, maintaining the potential of the Q node at a logic high level after the emission signal of the low potential voltage is output;   one end of the second capacitor is connected to the gate electrode of the eighth transistor, and the first emission clock signal is applied to another end of the second capacitor through the eighth transistor; and   the third capacitor has one end connected to the gate electrode of the seventh transistor, another end connected to one electrode of the seventh transistor and one electrode of the tenth transistor, and the high potential voltage is applied to the another end of the third capacitor, maintaining a potential of the gate electrode of the seventh transistor at a logic high level after the emission signal of the high potential voltage is output.