Subcutaneous insertable cardiac monitor optimized for electrocardiographic (ecg) data acquisition and processing

Abstract

Long-term electrocardiographic and physiological monitoring over a period lasting up to several years in duration can be provided through a continuously-recording subcutaneous insertable cardiac monitor (ICM). The sensing circuitry and the physical layout of the electrodes are specifically optimized to capture electrical signals from the propagation of low amplitude, relatively low frequency content cardiac action potentials, particularly the P-waves that are generated during atrial activation. In general, the ICM is intended to be implanted centrally and positioned axially and slightly to either the left or right of the sternal midline in the parasternal region of the chest. Additionally, the ICM includes an ECG sensing circuit that measures raw cutaneous electrical signals and performs signal processing prior to outputting the processed signals for sampling and storage.

What is claimed is: 
     
         1 . A subcutaneous insertable cardiac monitor optimized for electrocardiographic (ECG) data acquisition and processing, comprising:
 an implantable housing that is suitable for implantation within a living body;   at least one pair of ECG sensing electrodes; and   electronic circuitry provided at least partially within the implantable housing, the electronic circuitry comprising:
 a microcontroller operable to execute under modular micro-program control as specified in firmware; 
 an ECG front end circuit interfaced to the microcontroller and comprising a plurality of stages, the ECG front end configured to capture cardiac action potentials sensed by at least the pair of ECG sensing electrodes and to output an analog ECG signal, the stages further comprising:
 a unity voltage gain stage comprising an operational amplifier maintains a voltage of the sensed cardiac action potentials and increases a current of the sensed cardiac action potentials to feed at least one of the remaining stages; and 
 a passive high pass filtering stage directly following the unity voltage gain stage and configured to remove from the sensed cardiac action potential current baseline wonder and any offset generated during the unity gain stage, the passive high pass filtering stage comprising an AC coupling capacitor and a resistor; and 
 
 a memory electrically interfaced with the microcontroller and operable to store samples of the analog ECG signal. 
   
     
     
         2 . A monitor according to  claim 1 , the ECG front end circuit further comprising:
 a passive input filter stage preceding the unity gain voltage stage and comprising a further coupling capacitor and a termination resistor and a filter capacitor directly following the AC coupling capacitor.   
     
     
         3 . A monitor according to  claim 2 , wherein the passive input filtering stage shifts frequency response poles downwards in a presence of a high electrode impedance on from the patient, which reduces high frequency noise in the current. 
     
     
         4 . A monitor according to  claim 2 , the ECG front end circuit further comprising a voltage amplification and active filtering stage directly following the passive input filter stage and that is configured to amplify the voltage of the sensed cardiac action potentials while applying a low pass filter. 
     
     
         5 . A monitor according to  claim 4 , the ECG front end circuit an anti-aliasing low pass filter directly following the voltage amplification and active filtering stage and configured to apply an anti-aliasing filter to the current of the sensed cardiac action potentials. 
     
     
         6 . A monitor according to  claim 5 , wherein the anti-aliasing low pass filter comprises a resistor followed by an additional capacitor. 
     
     
         7 . A monitor according to  claim 1 , wherein the AC coupling capacitor directly follows the operational amplifier and wherein the AC coupling capacitor directly following the operational amplifier increases signal fidelity. 
     
     
         8 . A monitor according to  claim 1 , wherein the microcontroller configured to obtain the samples. 
     
     
         9 . A monitor according to  claim 8 , further comprising a wireless transceiver configured to wirelessly offload the samples from the memory. 
     
     
         10 . A monitor according to  claim 9 , wherein the wireless transceiver is further configured to receive commands for reprogramming of the firmware. 
     
     
         11 . A subcutaneous implantable recorder for optimized for electrocardiographic (ECG) data acquisition and processing, comprising:
 an implantable housing comprised of a biocompatible material that is suitable for implantation within a living body of a patient;   at least two of ECG sensing electrodes;   a power source; and   electronic circuitry provided within the housing, the electronic circuitry comprising:
 a microcontroller operable to execute under modular micro-program control as specified in firmware; 
   electronic circuitry provided at least partially within the implantable housing, the electronic circuitry comprising:
 a microcontroller operable to execute under modular micro-program control as specified in firmware; 
 an ECG front end circuit interfaced to the microcontroller and comprising a plurality of stages, the ECG front end configured to capture cardiac action potentials sensed by at least the pair of ECG sensing electrodes and to output an analog ECG signal, the stages further comprising:
 a unity voltage gain stage comprising an operational amplifier maintains a voltage of the sensed cardiac action potentials and increases a current of the sensed cardiac action potentials to feed at least one of the remaining stages; and 
 a passive high pass filtering stage directly following the unity voltage gain stage and configured to remove from the sensed cardiac action potential current baseline wonder and any offset generated during the unity gain stage, the passive high pass filtering stage comprising an AC coupling capacitor and a resistor; and 
 
 a memory electrically interfaced with the microcontroller and operable to store samples of the analog ECG signal. 
   
     
     
         12 . A recorder according to  claim 11 , the ECG front end circuit further comprising:
 a passive input filter stage preceding the unity gain voltage stage and comprising a further coupling capacitor and a termination resistor and a filter capacitor directly following the AC coupling capacitor.   
     
     
         13 . A recorder according to  claim 12 , wherein the passive input filtering stage shifts frequency response poles downwards in a presence of a high electrode impedance on from the patient, which reduces high frequency noise in the current. 
     
     
         14 . A recorder according to  claim 12 , the ECG front end circuit further comprising a voltage amplification and active filtering stage directly following the passive input filter stage and that is configured to amplify the voltage of the sensed cardiac action potentials while applying a low pass filter. 
     
     
         15 . A recorder according to  claim 14 , the ECG front end circuit an anti-aliasing low pass filter directly following the voltage amplification and active filtering stage and configured to apply an anti-aliasing filter to the current of the sensed cardiac action potentials. 
     
     
         16 . A recorder according to  claim 15 , wherein the anti-aliasing low pass filter comprises a resistor followed by an additional capacitor. 
     
     
         17 . A recorder according to  claim 11 , wherein the AC coupling capacitor directly follows the operational amplifier and wherein the AC coupling capacitor directly following the operational amplifier increases signal fidelity. 
     
     
         18 . A recorder according to  claim 11 , wherein the microcontroller configured to obtain the samples. 
     
     
         19 . A recorder according to  claim 18 , further comprising a wireless transceiver configured to wirelessly offload the samples from the memory. 
     
     
         20 . A recorder according to  claim 19 , wherein the wireless transceiver is further configured to receive commands for reprogramming of the firmware.