US2023284533A1PendingUtilityA1

Piezoelectric composite substrate and method for manufacturing same

Assignee: SHINETSU CHEMICAL COPriority: May 8, 2020Filed: Apr 28, 2021Published: Sep 7, 2023
Est. expiryMay 8, 2040(~13.8 yrs left)· nominal 20-yr term from priority
H10W 10/181H10P 90/1916H10P 90/1914H10N 30/073H03H 9/02574H03H 9/02559H10N 30/072H03H 9/02834H03H 3/08H10N 30/853
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Claims

Abstract

Provided are a piezoelectric substrate and a manufacturing method thereof, by which bonding strength enough for forming a piezoelectric layer on an insulating substrate having a significantly small linear expansion coefficient can be obtained through ion implantation even by heat treatment at 100° C. or less. A piezoelectric composite substrate 10 having successively stacked insulating substrate 2 , interlayer 3 , and piezoelectric layer 1 a is manufactured by laminating a piezoelectric single-crystal substrate surface having an ion implantation layer 1 a thereon and an insulating substrate 2 having a linear expansion coefficient less than that of the piezoelectric single-crystal substrate 1 with a difference in a range of 14×10 −6 /K to 16×10 −6 /K via the interlayer 3 to obtain a bonded body 4 , and after heat treatment, leaving the ion implantation layer 1 a as a piezoelectric layer and releasing the remaining portion 1 b of the piezoelectric single-crystal substrate from the bonded body 4 . The insulating substrate 2 and the interlayer 3 are each made of a Si-containing amorphous material.

Claims

exact text as granted — not AI-modified
1 . A piezoelectric composite substrate comprising an insulating substrate, an interlayer, and a piezoelectric layer stacked successively, wherein the piezoelectric layer has a thickness in a range of 100 nm to 2,000 nm in a stacking direction, the insulating substrate has a diameter in a range of 2 inches to 12 inches and a plate thickness of 100 μm to 2,000 μm, the insulating substrate has a linear expansion coefficient smaller than that of the piezoelectric layer with a difference therebetween in a range of 14×10 −6 /K to 16×10 −6 /K, and the insulating substrate and the interlayer each have a Si-containing amorphous material. 
     
     
         2 . The piezoelectric composite substrate according to  claim 1 , wherein the piezoelectric layer comprises lithium tantalate or lithium niobate. 
     
     
         3 . The piezoelectric composite substrate according to  claim 1 , wherein the insulating substrate is a quartz substrate. 
     
     
         4 . The piezoelectric composite substrate according to  claim 1 , wherein the interlayer comprises amorphous silicon or silicon dioxide. 
     
     
         5 . A method of manufacturing a piezoelectric composite substrate having an insulating substrate, an interlayer, and a piezoelectric layer stacked successively, comprising the steps of:
 preparing a piezoelectric single-crystal substrate and an insulating substrate having a linear expansion coefficient less than that of the piezoelectric single-crystal substrate with a difference therebetween falling within a range of 14×10 −6 /K to 16×10 −6 /K, and having a Si-containing amorphous material;   subjecting a surface of the piezoelectric single-crystal substrate to be laminated to ion implantation treatment to form an ion implantation layer in the piezoelectric single-crystal substrate;   forming an interlayer with a Si-containing amorphous material on one or both of the respective surfaces of the insulating substrate and the piezoelectric single-crystal substrate to be laminated;   laminating the surface of the insulating substrate to be laminated with the surface of the piezoelectric single-crystal substrate to be laminated via the interlayer to obtain a bonded body;   heat treating the bonded body; and   leaving the ion implantation layer as a piezoelectric layer and releasing the remaining portion of the piezoelectric single-crystal substrate from the heat-treated bonded body.   
     
     
         6 . The method of manufacturing a piezoelectric composite substrate according to  claim 5 , wherein in the step of forming the interlayer, the Si-containing amorphous material contains amorphous silicon or silicon dioxide and the interlayer is formed by CVD, sputtering, or spin coating.

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