Amplifier with parasitic capacitance neutralization

Abstract

Amplification circuitry is disclosed that couples neutralization transistors to amplification transistors to neutralize parasitic capacitance of the amplification transistors. Gates of a first amplification transistor and a first neutralization transistor are coupled together, and gates of a second amplification transistor and a second neutralization transistor are also coupled together. Drains of the first amplification transistor and the second neutralization transistor are coupled together, and drains of the second amplification transistor and the first neutralization transistor are also coupled together. Sources of neutralization transistors are coupled together at a node, such that a voltage swing of a first signal in the first neutralization transistor may be canceled by a voltage swing of a second signal in the second neutralization transistor. The node also couples to a resistor that prevents charge building in the neutralization transistors.

1 . (canceled) 
     
     
         2 . An electronic device comprising:
 an antenna; and   a transceiver communicatively coupled to the antenna, the transceiver comprising a plurality of amplifiers, each amplifier of the plurality of amplifiers comprising   a first transistor configured to amplify a signal,   a second transistor configured to neutralize a first parasitic capacitance associated with the first transistor via a first neutralization capacitance, and   a resistive element coupled to a source of the second transistor.   
     
     
         3 . The electronic device of  claim 2 , wherein each amplifier of the plurality of amplifiers comprises
 a third transistor configured to amplify the signal, and   a fourth transistor configured to neutralize a second parasitic capacitance associated with the third transistor via a second neutralization capacitance, wherein the fourth transistor comprises a source coupled to a source of the third transistor.   
     
     
         4 . The electronic device of  claim 3 , wherein the second transistor comprises
 a gate coupled to a gate of the first transistor, and   a drain coupled to a drain of the third transistor.   
     
     
         5 . The electronic device of  claim 3 , wherein the fourth transistor comprises
 a gate coupled to a gate of the second transistor, and   a drain coupled to a drain of the first transistor.   
     
     
         6 . The electronic device of  claim 2 , wherein the resistive element is coupled to a ground. 
     
     
         7 . The electronic device of  claim 6 , wherein the resistive element is configured to block current flow from the source of the second transistor and a source of a third transistor to the ground, wherein the third transistor is configured to neutralize a second parasitic capacitance. 
     
     
         8 . The electronic device of  claim 2 , wherein the resistive element is coupled to a source of the first transistor. 
     
     
         9 . The electronic device of  claim 8 , wherein each amplifier of the plurality of amplifiers comprises a switch, the resistive element, and the source of the first transistor being coupled to the switch, and the switch being configured to enable a respective amplifier to amplify the signal. 
     
     
         10 . The electronic device of  claim 9 , wherein the switch comprises a metal oxide semiconductor field-effect transistor (MOSFET). 
     
     
         11 . Amplification circuitry comprising:
 a plurality of amplification transistors, each amplification transistor of the plurality of amplification transistors configured to amplify a signal;   a plurality of neutralization transistors, each neutralization transistor of the plurality of neutralization transistors coupled to a respective amplification transistor of the plurality of amplification transistors and configured to neutralize a parasitic capacitance associated with the respective amplification transistor; and   a resistive element coupled to a plurality of sources of the plurality of neutralization transistors and a ground, the resistive element configured to block at least a portion of current flowing from the plurality of sources to the ground.   
     
     
         12 . The amplification circuitry of  claim 11 , wherein the amplification circuitry is configured to cancel a first voltage swing received at a first source of a first amplification transistor of the plurality of amplification transistors, a second source of a first neutralization transistor of the plurality of neutralization transistors, or both via a second voltage swing received at a third source of a second amplification transistor of the plurality of amplification transistors, a fourth source of a second neutralization transistor of the plurality of neutralization transistors, or both. 
     
     
         13 . The amplification circuitry of  claim 12 , wherein the first neutralization transistor comprises
 a first gate coupled to a second gate of the first amplification transistor, and   a first drain coupled to a second drain of the second amplification transistor.   
     
     
         14 . The amplification circuitry of  claim 13 , wherein the second neutralization transistor comprises
 a third gate coupled to a fourth gate of the second amplification transistor, and   a third drain coupled to a fourth drain of the first amplification transistor.   
     
     
         15 . The amplification circuitry of  claim 14 , wherein a first parasitic capacitance associated with the first amplification transistor is exhibited between the second gate of the first amplification transistor and the fourth drain of the first amplification transistor, and a second parasitic capacitance associated with the first neutralization transistor is exhibited between the first gate of the first neutralization transistor and the first drain of the first neutralization transistor. 
     
     
         16 . The amplification circuitry of  claim 14 , wherein a first parasitic capacitance of the second amplification transistor is exhibited between the first gate of the first amplification transistor and the second drain of the second amplification transistor, and a second parasitic capacitance associated with the second neutralization transistor is exhibited between third gate of the second neutralization transistor and the third drain of the second neutralization transistor. 
     
     
         17 . A transceiver, comprising:
 a plurality of amplifiers, each amplifier of the plurality of amplifiers comprising   a first transistor configured to amplify a signal,   a second transistor configured to neutralize a first parasitic capacitance associated with the first transistor, and   a resistive element coupled to a source of the second transistor and a ground, the resistive element configured to block at least a portion of current flowing from the source of the second transistor, and   a plurality of matching networks communicatively coupled to the plurality of amplifiers, the plurality of matching networks configured to absorb one or more parasitic capacitances associated with the first transistor, the second transistor, or both.   
     
     
         18 . The transceiver of  claim 17 , wherein, in operation, the second transistor exhibits a second parasitic capacitance between a gate of the second transistor and a drain of the second transistor, a third parasitic capacitance between the gate of the second transistor and a source of the second transistor, and a fourth parasitic capacitance between the drain of the second transistor and the source of the second transistor. 
     
     
         19 . The transceiver of  claim 18 , wherein a first matching network of the plurality of matching networks communicatively coupled to an amplifier of the plurality of amplifiers is configured to absorb the third parasitic capacitance, and a second matching network of the plurality of matching networks communicatively coupled to the amplifier is configured to absorb the fourth parasitic capacitance. 
     
     
         20 . The transceiver of  claim 19 , wherein each amplifier is configured to neutralize the first parasitic capacitance associated with the first transistor via the second parasitic capacitance. 
     
     
         21 . The transceiver of  claim 20 , wherein the resistive element comprises a variable resistor.