High Speed Semiconductor Devices

Abstract

Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device according to the present disclosure includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a gate cut feature adjacent the gate structure, a source/drain contact isolation feature adjacent the source/drain contact, a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and an air gap sandwiched between the spacer and the liner. The gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a fin extending from a substrate, the fin extending lengthwise along a direction and comprising a channel region and a source/drain region adjacent to the channel region;   a gate structure over the channel region;   a source/drain contact over the source/drain region;   a gate cut feature adjacent the gate structure;   a source/drain contact isolation feature adjacent the source/drain contact;   a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure;   a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and   an air gap sandwiched between the spacer and the liner,   wherein the gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the gate structure and the source/drain contact are separated by the air gap along the direction. 
     
     
         3 . The semiconductor device of  claim 1 , further comprising:
 a gate cap layer disposed on the gate structure; and   a source/drain cap layer disposed on the source/drain contact,   wherein the spacer also extends along a sidewall of the gate cap layer,   wherein the liner also extends along a sidewall of the source/drain cap layer.   
     
     
         4 . The semiconductor device of  claim 3 , wherein the gate cap layer and the source/drain cap layer comprise W, Co, Ni, Ru, Ti, Ta, TiN, or TaN. 
     
     
         5 . The semiconductor device of  claim 3 , further comprising:
 a first dielectric layer over the gate cap layer; and   a second dielectric layer over the source/drain cap layer,   wherein the spacer also extends along a sidewall of the first dielectric layer,   wherein the liner also extends along a sidewall of the second dielectric layer.   
     
     
         6 . The semiconductor device of  claim 5 , further comprising:
 a gate contact via extending through the first dielectric layer to electrically coupled to the gate cap layer; and   a source/drain contact via extending through the second dielectric layer to electrically couple to the source/drain contact,   wherein, along the direction, the gate contact via is spaced apart from the spacer by a portion of the first dielectric layer,   wherein, along the direction, the source/drain contact via is spaced apart from the liner by a portion of the second dielectric layer.   
     
     
         7 . The semiconductor device of  claim 6 , wherein, along the direction, the gate contact via is spaced apart from the source/drain contact via by the spacer, the liner, and the air gap. 
     
     
         8 . The semiconductor device of  claim 1 , further comprising a plug feature over the air gap between the spacer and the liner. 
     
     
         9 . The semiconductor device of  claim 1 , wherein top surfaces of the gate cut feature, the source/drain contact isolation feature, the liner, and the spacer are coplanar. 
     
     
         10 . A semiconductor structure, comprising:
 an active region extending lengthwise along a first direction and comprising a channel region and a source/drain region adjacent to the channel region;   a gate structure over the channel region;   a source/drain contact over the source/drain region;   a gate cut feature adjacent the gate structure along a second direction perpendicular to the first direction;   a source/drain contact isolation feature adjacent the source/drain contact along a second direction perpendicular to the first direction;   a first sealing feature over the gate structure;   a second sealing feature over the source/drain contact;   a spacer extending along a sidewall of the gate cut feature, a sidewall of the first sealing feature and a sidewall of the gate structure;   a liner extending along a sidewall of the source/drain contact isolation feature, a sidewall of the second sealing feature and a sidewall of the source/drain contact; and   an air gap sandwiched between the spacer and the liner.   
     
     
         11 . The semiconductor structure of  claim 10 , wherein the gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner. 
     
     
         12 . The semiconductor structure of  claim 10 ,
 wherein the gate cut feature comprises a first inner layer and a first outer layer,   wherein a composition of the first outer layer is the same as a composition of the first sealing feature,   wherein the first inner layer is spaced apart from the spacer by the first outer layer.   
     
     
         13 . The semiconductor structure of  claim 12 , wherein the gate cut feature comprises a first air pocket trapped in the first inner layer. 
     
     
         14 . The semiconductor structure of  claim 10 ,
 wherein the source/drain contact isolation feature comprises a second inner layer and a second outer layer,   wherein a composition of the second outer layer is the same as a composition of the second sealing feature,   wherein the second inner layer is spaced apart from the liner by the second outer layer.   
     
     
         15 . The semiconductor structure of  claim 14 , wherein the source/drain contact isolation feature comprises a second air pocket trapped in the second inner layer. 
     
     
         16 . The semiconductor structure of  claim 10 , further comprising:
 a gate cap layer sandwiched directly between the gate structure and the first sealing feature; and   a source/drain cap layer sandwiched directly between the source/drain contact and the second sealing feature.   
     
     
         17 . A method of forming a semiconductor device, comprising:
 receiving a workpiece comprising:
 a substrate, 
 a fin extending from the substrate, the fin comprising a channel region and a source/drain region adjacent to the channel region, 
 a gate structure over the channel region, 
 a plurality of first spacers and a plurality of second spacers, wherein the gate structure is sandwiched between two of the plurality of first spacers, the two of the plurality of first spacers are sandwiched between two of the plurality of second spacers, 
 a source/drain contact over the source/drain region, 
 a plurality of liners, wherein the source/drain contact is sandwiched between two of the plurality of liners; 
   forming a gate contact via over and electrically coupled to the gate structure;   forming a source/drain contact via over the source/drain contact; and   after the forming of the source/drain contact via, selectively removing the plurality of second spacers to form air gaps extending between the gate contact via and the source/drain contact via.   
     
     
         18 . The method of  claim 17 , further comprising forming a first sealing layer over the workpiece. 
     
     
         19 . The method of  claim 18 , further comprising forming a second sealing layer over the first sealing layer. 
     
     
         20 . The method of  claim 19 , furthering comprising forming a first sealing layer over the workpiece using a first deposition process and forming a second sealing layer over the first sealing layer using a second deposition process, wherein the first deposition process is different from the second deposition process.