Integrated circuit with non-preferred direction curvilinear wiring

Abstract

Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

1 . An integrated circuit comprising:
 a first plurality of wiring layers with no preferred wiring direction and curvilinear wiring; and   a second plurality of wiring layers with at least first and second preferred wiring directions.   
     
     
         2 . The IC of  claim 1 , wherein the first plurality of wiring layers comprises layers 3 and 4, and the second plurality of wiring layers comprises layers 5 and 6. 
     
     
         3 . The IC of  claim 2 , wherein the second plurality of wiring layers further comprises layers 1 and 2. 
     
     
         4 . The IC of  claim 1 , wherein the first plurality of wiring layers comprises layers 1-4, and the second plurality of wiring layers comprises layers 5 and 6. 
     
     
         5 . The IC of  claim 1 , wherein the second plurality of wiring layers comprises wiring layers 1 and 2. 
     
     
         6 . The IC of  claim 5 , wherein the wiring layers 1 and 2 each has a plurality of regions with preferred direction rectilinear wiring for pre-defined IP (intellectual property) circuit blocks. 
     
     
         7 . The IC of  claim 6 , wherein a plurality of curvilinear wire segments are defined on wiring layers 1 and 2 between the regions with PD wiring for the IP circuit blocks. 
     
     
         8 . The IC of  claim 1 , wherein each preferred wiring direction is a horizontal direction or a vertical direction, and the preferred wiring directions of different adjacent layers in the second plurality of layers alternate between horizontal and vertical directions. 
     
     
         9 . The IC of  claim 1 , wherein preferred wiring direction on each layer is the direction that includes at least 90% of the wiring on that layer. 
     
     
         10 . The IC of  claim 1 , wherein at least one layer in the first plurality of layers comprises wires traversing in more than eight directions. 
     
     
         11 . The IC of  claim 1 , wherein wiring on the first plurality of wiring layers is defined with a non-preferred direction (NPD) first router that defines NPD routes in an IC design that is used to manufacture the IC, while wiring on the second plurality of wiring layers are defined by a preferred direction (PD) second router that defines PD routes in the IC. 
     
     
         12 . The IC of  claim 11 , wherein the PD second router assesses a penalty cost for segments of the routes that traverse along one or more non-preferred directions of the second plurality of wiring layers. 
     
     
         13 . The IC of  claim 12 , wherein the PD second router does not assess a penalty cost for segments of routes that traverse along one or more preferred directions of each wiring layer in the second plurality of wiring layers. 
     
     
         14 . The IC of  claim 11 , wherein the NPD first router defines a plurality of curvilinear edges on the first plurality of wiring layers. 
     
     
         15 . The IC of  claim 14 , wherein the PD second router does not define any curvilinear edges on the second plurality of wiring layers. 
     
     
         16 . The IC of  claim 1 , wherein a router defines the wiring on the first plurality of wiring layers without identifying 8 or less wiring directions as preferred wiring directions, while defining the wiring on the second plurality of wiring layers by identifying one or more wiring directions on each of wiring layer in the second plurality of wiring layers as preferred directions of those layers. 
     
     
         17 . The IC of  claim 16 , wherein the router defines the wiring on the first plurality of wiring layers without imposing any penalty cost for route segments along nine or more wiring directions on each wiring layer of the first plurality of wiring layers, while defining the wiring on the second plurality of wiring layers by imposing a penalty cost for route segments along any direction on any layer in the second plurality of layers that is not one of the preferred wiring directions of that layer. 
     
     
         18 . The IC of  claim 17 , wherein the router defines the wiring on the first plurality of wiring layers without imposing any penalty cost for route segments along any wiring direction on each wiring layer of the first plurality of wiring layers. 
     
     
         19 . The IC of  claim 17 , wherein the router defines a plurality of routes each with at least one router-defined curvilinear segment on the first plurality of wiring layers but does not define any routes with any router-defined curvilinear segment on the second plurality of wiring layers. 
     
     
         20 . The IC of  claim 1 , wherein the first plurality of non-preferred direction wiring layers include shorter wires that serve as shorter connections for connecting different locations on a substrate of the IC, while the second plurality of preferred direction wiring layer include longer wires that serve as longer connections for connecting different locations on the IC substrate.