Semiconductor memory device and memory system

Abstract

A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.

1 . A semiconductor memory device comprising:
 a plurality of memory cells each capable of storing data using n levels of threshold voltages, where n is an integer of 3 or more, the n levels of threshold voltages comprising a first level, a second level higher than the first level, and a third level higher than the second level, and the memory cells including first to fourth memory cells; and   a word line connected to the first to fourth memory cells such that the first to fourth memory cells are collectively subject to a write operation including a plurality of program operations and a plurality of verify operations, each program operation including applying a program voltage to the word line, and each verify operation including applying a read voltage lower than the program voltage to the word line,   wherein, when performing the write operation to the first to fourth memory cells from a state where a threshold voltage of each of the first to fourth memory cells is the first level,   the plurality of program operations comprise:
 a first program operation for increasing the threshold voltage of the first memory cell toward the second level with a first magnitude; 
 a second program operation for increasing the threshold voltage of the second memory cell toward the second level with a second magnitude lower than the first magnitude; 
 a third program operation for increasing the threshold voltage of the third memory cell toward the third level with a third magnitude; and 
 a fourth program operation for increasing the threshold voltage of the fourth memory cell toward the third level with a fourth magnitude lower than the third magnitude, and 
   the plurality of verify operations comprise:
 a first verify operation for a first verify level lower than a level lower than the second level; 
 a second verify operation for a second verify level same as the second level; 
 a third verify operation for a third verify level lower than the third level; and 
 a fourth verify operation for a fourth verify level same as the third level.