Semiconductor memory structure and method of manufacturing the same

Abstract

A semiconductor memory structure and a method of manufacturing a semiconductor memory structure are provided. The semiconductor memory structure includes alternatively arranged stacking portions and cell regions. Each cell region includes two ferroelectric layers formed along the adjacent stacking portions; and at least one central portion disposed between the ferroelectric layers and includes a first conductive structure and a second conductive structure separated by a channel isolation structure as well as two semiconductor layers formed along the ferroelectric layers. The first conductive structure includes a contact portion and an extension portion. The contact portion is disposed between the semiconductor layers. The extension portion extends from the contact portion to the channel isolation structure and is separated from the semiconductor layers through dielectric layers.

1 . A method of manufacturing a semiconductor memory structure, the method comprising:
 forming a stack of alternating insulating layers and sacrificial layers over a substrate;   forming a plurality of trenches in the stack;   replacing the sacrificial layers with first conductive layers;   filling each of the plurality of trenches with a multi-layered structure including a ferroelectric layer, a semiconductor layer, and a dielectric layer;   removing portions of the multi-layered structure to leave remaining portions, so that the remaining portion is disposed between two semiconductor layers of two adjacent multi-layered structures of the multi-layered structures and comprises two dielectric layers formed separately along the two semiconductor layers;   forming cell isolation structures between the ferroelectric layers of each two adjacent multi-layered structures of the multi-layered structures and forming channel isolation structures between the semiconductor layers of each two adjacent multi-layered structures of the multi-layered structures; and   forming first conductive structures and second conductive structures, wherein each of the first conductive structures is disposed between one of the cell isolation structures and an adjacent channel isolation structure of the channel isolation structures, and each of the second conductive structures is disposed between one of the cell isolation structures and the other adjacent channel isolation structure of the channel isolation structures,   wherein the first conductive structures partially contact the semiconductor layers and partially contact the dielectric layers.   
     
     
         2 . The method of  claim 1 , wherein replacing the sacrificial layers with first conductive layers comprises:
 replacing materials disposed between the dielectric layers in the remaining portions with conductive materials to form extension portions of the first conductive structures; and   replacing materials disposed between the remaining portions and the cell isolation structures with the conductive materials to form contact portions, wherein the extension portion extends from one of the contact portion to one of the channel isolation structures and is separated from the semiconductor layers through the dielectric layers.   
     
     
         3 . The method of  claim 1 , wherein each of the contact portions of the first conductive structures has a contact area contacting the semiconductor layers, each of the second conductive structures has a contact area contacting the semiconductor layers, and the contact area of the contact portion of the first conductive structure and the contact area of the second conductive structure are similar. 
     
     
         4 . The method of  claim 1 , wherein after the remaining portions are formed, portions of the ferroelectric layer and portions of the semiconductor layer are removed from bottoms of the plurality of trenches to expose the substrate from the plurality of trenches. 
     
     
         5 . The method of  claim 4 , wherein both of ferroelectric layer and semiconductor layer have an L-shaped vertical cross section formed along sidewalls of the plurality of trenches and partially covering the bottoms of the plurality of trenches whereby the substrate exposes from the plurality of trenches. 
     
     
         6 . The method of  claim 1 , wherein replacing the sacrificial layers with first conductive layers through the plurality of trenches further comprises:
 forming a plurality first recesses by partially removing the sacrificial layers; and   forming glue layers along sidewalls of the plurality first recesses before forming the first conductive layers.   
     
     
         7 . The method of  claim 6 , wherein the glue layers comprise oxides. 
     
     
         8 . A method of manufacturing a semiconductor memory structure, the method comprising:
 forming a stack of alternating insulating layers and sacrificial layers over a substrate;   forming a plurality of first trenches in the stack;   replacing the sacrificial layers with conductive layers;   sequentially depositing a ferroelectric layer, a semiconductor layer and a dielectric layer along sidewalls and a bottom of each of the plurality of first trenches;   removing portions of the dielectric layer, portions of the semiconductor layer and portions of the ferroelectric layer to expose the substrate from the plurality of first trenches;   filling the plurality of first trenches with a first sacrificial material;   forming a plurality of second trenches in the stack, wherein the plurality of second trenches and the plurality of first trench are arranged alternately;   sequentially depositing a ferroelectric layer, a semiconductor layer and a dielectric layer along sidewalls and a bottom of each of the plurality of second trenches;   removing portions of the dielectric layer, portions of the semiconductor layer and portions of the ferroelectric layer to expose the substrate from the second trench; filling each of the plurality of second trench with a second sacrificial material; removing portions of the first sacrificial material, portions of the second sacrificial material, and portions of the dielectric layer to form a plurality of third trenches and a plurality of remaining portions, wherein the plurality of third trenches and the plurality of remaining portions are arranged alternately, and wherein the each of the plurality of remaining portion is disposed between two semiconductor layers and comprises the dielectric layers formed separately along the two semiconductor layers;   filling the plurality of third trenches with a third sacrificial material;   removing portions of the third sacrificial material to form a plurality of channel isolation trenches so that one side of each of the plurality of remaining portions and the two semiconductor layers are exposed from the plurality of channel isolation trenches;   filling the plurality of channel isolation trenches with isolation materials to form channel isolation structures;   removing portions of the third sacrificial materials and the semiconductor layers to form cell isolation trenches so that the third sacrificial materials is divided into two parts, wherein one part of the third sacrificial materials next to the remaining portion is replaced with conductive materials to form a contact portion, and the other part of the third sacrificial materials next to the channel isolation structure is replaced with conductive materials to form a conductive structure;   filling the cell isolation trenches with isolation materials to form cell isolation structure; and   replacing the first and second sacrificial materials in the remaining portions with conductive materials to form an extension portion.   
     
     
         9 . The method of  claim 8 , wherein the extension portion extends from the contact portion to the channel isolation structure and is separated from the two semiconductor layers through the dielectric layers. 
     
     
         10 . The method of  claim 9 , wherein the channel isolation structure has a length equal to or less than a length of the extension portion. 
     
     
         11 . The method of  claim 9 , wherein the contact portion has a contact area contacting the two semiconductor layers, the second conductive structure has a contact area contacting the two semiconductor layers, and the contact area of the contact portion and the contact area of the conductive structure are similar. 
     
     
         12 . The method of  claim 9 , wherein the extension portion has a length from the contact portion to the channel isolation structure, which is 10% to 90% of a length of each of the two semiconductor layers. 
     
     
         13 . The method of  claim 9 , wherein the contact portion and the extension portion present a T-shape top view. 
     
     
         14 . The method of  claim 8 , wherein each of the ferroelectric layers has an L-shaped vertical cross section. 
     
     
         15 . The method of  claim 8 , wherein each of the two semiconductor layers has an L-shaped vertical cross section. 
     
     
         16 . A method of manufacturing a semiconductor memory structure, the method comprising:
 forming a stack of alternating insulating layers and conductive layers over a substrate, wherein the stack has a plurality of first trenches;   filling each of the plurality of first trenches with a multi-layered structure including a ferroelectric layer, a semiconductor layer, a dielectric layer, and first sacrificial materials;   removing portions of the multi-layered structure to form a plurality of second trenches and a plurality of remaining portions, wherein the remaining portion is disposed between two semiconductor layers of two adjacent multi-layered structures of the multi-layered structures and comprises two dielectric layers formed separately along the two semiconductor layers;   filling the plurality of second trenches with second sacrificial materials;   forming cell isolation structures and channel isolation structures by removing portions of the second sacrificial materials, wherein the cell isolation structures are positioned between the ferroelectric layers of each two adjacent multi-layered structures of the multi-layered structures and the channel isolation structures are positioned between the semiconductor layers of each two adjacent multi-layered structures of the multi-layered structures;   forming first conductive structures and second conductive structures by replacing the second sacrificial materials in the remaining portions and in the plurality of second trenches with conductive materials, wherein each of the first conductive structures is disposed between one of the cell isolation structures and an adjacent channel isolation structure of the channel isolation structures, and each of the second conductive structures is disposed between one of the cell isolation structures and the other adjacent channel isolation structure of the channel isolation structures.   
     
     
         17 . The method of  claim 16 , wherein forming the first conductive structures comprises:
 replacing the second sacrificial materials disposed between the dielectric layers in the remaining portions with conductive materials to form extension portions of the first conductive structures; and   replacing the second sacrificial materials disposed between the remaining portions and the cell isolation structures with the conductive materials to form contact portions, wherein the extension portion extends from one of the contact portion to one of the channel isolation structures and is separated from the semiconductor layers through the dielectric layers.   
     
     
         18 . The method of  claim 17 , wherein the channel isolation structure has a length equal to or less than a length of the extension portion; and the extension portion has a length from the contact portion to the channel isolation structure, which is 10% to 90% of a length of each of the two semiconductor layers. 
     
     
         19 . The method of  claim 16 , wherein each of the conductive layer comprises two sublayers and a glue layer; and the glue layer is disposed between the conductive layer and an adjacent insulating layer of the insulating layers. 
     
     
         20 . The method of  claim 19 , wherein the glue layer comprises oxides.