Shoot-through current limiting circuit

Abstract

Aspects of the disclosure provide for a circuit. In at least some examples, the circuit includes a logic circuit, a first comparator, a second comparator, and an AND logic circuit. The logic circuit has an output and the first comparator has a first input coupled to an input voltage (VIN) pin, a second input configured to receive a Vin under voltage lockout (VINUVLO) threshold value, and an output. The second comparator has a first input coupled to a power middle (PMID) pin, a second input coupled to a battery pin, and an output and the AND logic circuit has a first input coupled to the output of the logic circuit, a second input coupled to the output of the first comparator, a third input coupled to the output of the second comparator, and an output coupled to an input of a field-effect transistor (FET) control circuit.

What is claimed is: 
     
         1 . A method for operating a battery charging circuit, comprising:
 receiving a request to enter a low-power mode;   comparing an input voltage at an input voltage terminal to an input voltage threshold;   comparing a voltage at a power middle terminal to a battery voltage at a battery terminal; and   entering the low-power mode in response to the input voltage being higher than the input voltage threshold and the voltage at the power middle terminal being lower than the battery voltage, and not entering the low-power mode responsive to either the input voltage being lower than the input voltage threshold or the voltage at the power middle terminal being higher than the battery voltage.   
     
     
         2 . The method of  claim 1 , further comprising disconnecting the input voltage terminal or the battery terminal from the battery charging circuit responsive to entering the low-power mode. 
     
     
         3 . The method of  claim 2 , wherein disconnecting the input voltage terminal or the battery terminal from the battery charging circuit includes controlling one or more transistors to enter a non-conductive state. 
     
     
         4 . The method of  claim 3 , wherein a first comparator provides a logic high output responsive to the input voltage being higher than the input voltage threshold, and a second comparator provides a logic high output responsive to the voltage at the power middle terminal being lower than the battery voltage. 
     
     
         5 . The method of  claim 1 , wherein the request to enter the low-power mode is generated based on input received from a user. 
     
     
         6 . The method of  claim 3 , wherein the transistors being controlled are field effect transistors (FETs). 
     
     
         7 . A method for battery charging comprising:
 configuring a first logic circuit to provide a request signal at a first logic output;   coupling a first comparator input to an input voltage terminal, and coupling a second comparator input to an input voltage threshold terminal to provide a first comparator output signal at a first comparator output;   coupling a third comparator input to a power middle (PMID) terminal, and coupling a fourth comparator input to a battery terminal to provide a second comparator output signal at a second comparator output; and   providing a low-power mode enable signal at a second logic output of a second logic circuit, wherein a first input of the second logic circuit is coupled to the first logic output, a second input of the second logic circuit is coupled to the first comparator output, a third input of the second logic circuit is coupled to the second comparator output.   
     
     
         8 . The method of  claim 7 , wherein the second logic circuit provides the low-power mode enable signal responsive to a first signal at the first comparator output and a second signal at the second comparator output each being asserted. 
     
     
         9 . The method of  claim 7 , further comprising coupling a buffer between the battery terminal and the fourth comparator input. 
     
     
         10 . The method of  claim 8 , further comprising:
 coupling a first gate of a first transistor to a transistor control circuit, and coupling a current terminal of the first transistor to the input voltage terminal; and   coupling a second gate of a second transistor to the transistor control circuit, coupling a first current terminal of the second transistor to the PMID terminal, and coupling a second current terminal of the second transistor to a second current terminal of the first transistor.   
     
     
         11 . The method of  claim 10 , wherein the first and second transistors are each n-type field effect transistors (nFETs). 
     
     
         12 . The method of  claim 10 , wherein the transistor control circuit controls the first and second transistors responsive to the second logic output. 
     
     
         13 . The method of  claim 12 , further comprising coupling a third gate terminal of a third transistor to the transistor control circuit, coupling a first current terminal of the third transistor to the PMID terminal, and coupling a second current terminal of the third transistor to the battery terminal. 
     
     
         14 . The method of  claim 13 , wherein the third transistor is a p-type field effect transistor (pFET). 
     
     
         15 . The method of  claim 14 , wherein the transistor control circuit controls the third transistor responsive to the second logic output.