US2023275058A1PendingUtilityA1

Electronic substrate and electronic apparatus

Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPPriority: Oct 21, 2016Filed: May 5, 2023Published: Aug 31, 2023
Est. expiryOct 21, 2036(~10.2 yrs left)· nominal 20-yr term from priority
H10W 72/387H10W 72/334H10W 90/00H10W 74/131H10W 70/68H10W 90/22H10W 90/721H10W 90/724H10W 90/734H10W 90/701H10W 74/15H10W 74/012H10F 39/811H10F 39/804H01L 24/29H01L 23/13H01L 23/3157H01L 25/18H01L 27/14618H01L 27/14636H01L 2224/26175H01L 2224/29017
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Claims

Abstract

Provided is an electronic substrate that achieves a reduction in a size of a substrate and enables a void risk in an underfill to be reduced, and an electronic apparatus. The electronic substrate in one aspect of the present technology includes an electronic chip that is placed above the substrate, an electrode that exists between the substrate and the electronic chip and electrically connects the substrate and the electronic chip, the underfill with which a space between the substrate and the electronic chip is filled so that the electrode is sealed and protected, a protection target to be protected from inflow of the underfill, the protection target being formed on the substrate, and an underfill inflow prevention unit that is formed in the substrate so as to surround an entirety or a portion of the protection target.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An electronic substrate, comprising:
 an electronic chip above a substrate;   an electrode between the substrate and the electronic chip, wherein the electrode electrically connects the substrate and the electronic chip;   an underfill in a space between the substrate and the electronic chip to seal the electrode;   a protection target on the substrate; and   a first inflow prevention unit configured to prevent the underfill from flowing into the protection target, wherein the first inflow prevention unit includes a first recessed groove that surrounds the protection target on all sides of the protection target.   
     
     
         2 . The electronic substrate according to  claim 1 , further comprising an optical layer on a surface of the substrate. 
     
     
         3 . The electronic substrate according to  claim 2 , further comprising a second inflow prevention unit configured to prevent the underfill from flowing into the optical layer, wherein the second inflow prevention unit is between the electronic chip and the optical layer. 
     
     
         4 . The electronic substrate according to  claim 3 , wherein the second inflow prevention unit includes one of a second recessed groove or a protruding wall. 
     
     
         5 . The electronic substrate according to  claim 3 , wherein 
 the second inflow prevention unit includes a plurality of second recessed grooves,   a shape of each of the plurality of second recessed grooves is one of circular or rectangular, and   each of the plurality of second recessed grooves has a different size.   
     
     
         6 . The electronic substrate according to  claim 1 , wherein the first recessed groove has an inclination angle of 60° to 90° with respect to a surface of the substrate. 
     
     
         7 . The electronic substrate according to  claim 1 , wherein a ratio of a depth to a width of the first recessed groove ranges from 0.5 to 16000. 
     
     
         8 . The electronic substrate according to  claim 1 , wherein the protection target is a connection pad connected to an external equipment. 
     
     
         9 . The electronic substrate according to  claim 1 , further comprising a plurality of protection targets including the protection target, wherein the first inflow prevention unit is in the substrate so as to surround the protection target. 
     
     
         10 . The electronic substrate according to  claim 1 , wherein 
 the protection target is a light-receiving layer,   the electronic chip is a semiconductor chip including a functional circuit, and   the electronic substrate is a component of a solid-state image sensor.   
     
     
         11 . The electronic substrate according to  claim 10 , wherein a width of a flat portion between the underfill and the light-receiving layer ranges from λ/8 to 30λ with respect to a center wavelength λ of incident light that enters the light-receiving layer. 
     
     
         12 . The electronic substrate according to  claim 11 , wherein 
 the first recessed groove includes a plurality of recessed groove portions, and   an interval between each of the plurality of recessed groove portions has a nonidentical pitch.   
     
     
         13 . The electronic substrate according to  claim 12 , wherein the interval between the plurality of recessed groove portions ranges from λ/8 to 30λ with respect to the center wavelength λ of the incident light that enters the light-receiving layer. 
     
     
         14 . The electronic substrate according to  claim 12 , wherein a width of a first recessed groove portion of the plurality of recessed groove portions is different from a width of a second recessed groove portion of the plurality of recessed groove portions. 
     
     
         15 . The electronic substrate according to  claim 12 , wherein a width of each of the plurality of recessed groove portions ranges from λ/8 to 30λ with respect to the center wavelength λ of the incident light that enters the light-receiving layer. 
     
     
         16 . The electronic substrate according to  claim 1 , wherein 
 the protection target comprises a plurality of connection pads, and   the first inflow prevention unit surrounds the plurality of connection pads.   
     
     
         17 . The electronic substrate according to  claim 1 , wherein 
 the protection target comprises a plurality of connection pads,   the first inflow prevention unit further includes a second recessed groove,   the first recessed groove surrounds a first number of connection pads of the plurality of connection pads, and   the second recessed groove surrounds a second number of connection pads, greater than the first number of connection pads, of the plurality of connection pads.   
     
     
         18 . An electronic apparatus, comprising:
 an electronic substrate that comprises:
 an electronic chip above a substrate; 
 an electrode between the substrate and the electronic chip, wherein the electrode electrically connects the substrate and the electronic chip; 
 an underfill in a space between the substrate and the electronic chip to seal the electrode; 
 a protection target on the substrate; and 
 an inflow prevention unit configured to prevent the underfill from flowing into the protection target, wherein the inflow prevention unit includes a recessed groove that surrounds the protection target on all sides of the protection target.

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