Strobe-offset control circuit

Abstract

A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.

What is claimed is: 
     
         1 . (canceled) 
     
     
         2 . An integrated circuit (IC) memory controller, comprising:
 control circuitry that is responsive to a mode control signal to enter a calibration mode of operation;   a selector, while operating in the calibration mode of operation, to provide a strobe signal received from a memory to a delay circuit;   receiver circuitry, while operating in the calibration mode of operation, to compare a first edge position of the received strobe signal to a second edge position of a data signal accompanied by the strobe signal;   wherein for a calibration read operation performed while in the calibration mode of operation, the control circuitry is to detect a phase difference between a sample signal of the receiver circuitry and the data signal, the control circuitry to adjust an offset between the sample signal and the data signal based on the detected phase difference.   
     
     
         3 . The IC memory controller according to  claim 2 , wherein:
 the control circuitry is responsive to a state of a calibrate-enable signal to enter the calibration mode of operation.   
     
     
         4 . The IC memory controller according to  claim 2 , wherein:
 the control circuitry is to adjust the offset as an applied adjustment to the sample signal in response to detecting the phase difference.   
     
     
         5 . The IC memory controller according to  claim 2 , wherein:
 the control circuitry is to adjust the offset as an applied adjustment to the data signal in response to detecting the phase difference.   
     
     
         6 . The IC memory controller according to  claim 2 , further comprising:
 a transmit circuit to transmit a lock signal based on a threshold relative offset value.   
     
     
         7 . The IC memory controller according to  claim 6 , wherein:
 following transmitting of the lock signal by the transmitter, the control circuitry is to enter a receive mode of operation.   
     
     
         8 . The IC memory controller according to  claim 2 , further comprising:
 command generation circuitry to issue a calibration read command for the calibration read operation consistent with a dynamic random access memory (DRAM) protocol.   
     
     
         9 . The IC memory controller according to  claim 2 , wherein:
 the calibration read operation comprises a read request for calibration data that is independent of any data needs of a host that is in communication with the IC memory controller.   
     
     
         10 . The IC memory controller according to  claim 2 , wherein:
 the calibration mode of operation takes place during a system initialization.   
     
     
         11 . The IC memory controller according to  claim 2 , wherein:
 the calibration mode of operation takes place during a time interval where the memory is not utilized.   
     
     
         12 . A method of operation in an integrated circuit (IC) memory controller, the method comprising:
 entering a calibration mode of operation in response to a mode control signal;   while operating in the calibration mode of operation, providing a strobe signal received from a memory to a delay circuit;   while operating in the calibration mode of operation, comparing a first edge position of the received strobe signal to a second edge position of a data signal accompanied by the strobe signal;   wherein for a calibration read operation performed while in the calibration mode of operation, detecting a phase difference between a sample signal and the data signal, and adjusting an offset between the sample signal and the data signal based on the detected phase difference.   
     
     
         13 . The method according to  claim 12 , wherein:
 entering the calibration mode of operation is in response to a state of a calibrate-enable signal.   
     
     
         14 . The method according to  claim 12 , wherein adjusting the offset between the sample signal and the data signal comprises:
 adjusting the offset as an applied adjustment to the sample signal in response to detecting the phase difference.   
     
     
         15 . The method according to  claim 12 , wherein adjusting the offset between the sample signal and the data signal comprises:
 adjusting the offset as an applied adjustment to the data signal in response to detecting the phase difference.   
     
     
         16 . An integrated circuit (IC) chip, comprising:
 memory control circuitry, including
 a multiplexer, while operating in a calibration mode of operation, to provide a strobe signal received from a memory device to a delay circuit; 
 a receiver, while operating in the calibration mode of operation, to compare a first edge position of the received strobe signal to a second edge position of a data signal accompanied by the strobe signal; 
 wherein for a calibration read operation performed while in the calibration mode of operation, the memory control circuitry is to detect a phase difference between a sample signal of the receiver and the data signal, the memory control circuitry to adjust an offset between the sample signal and the data signal based on the detected phase difference. 
   
     
     
         17 . The IC chip according to  claim 16 , wherein:
 the memory control circuitry is responsive to a state of a calibrate-enable signal to enter the calibration mode of operation.   
     
     
         18 . The IC chip according to  claim 16 , wherein:
 the memory control circuitry is to adjust the offset as an applied adjustment to the sample signal in response to detecting the phase difference.   
     
     
         19 . The IC chip according to  claim 16 , wherein:
 the memory control circuitry is to adjust the offset as an applied adjustment to the data signal in response to detecting the phase difference.   
     
     
         20 . The IC chip according to  claim 16 , further comprising:
 a transmit circuit to transmit a lock signal based on a threshold relative offset value.   
     
     
         21 . The IC chip according to  claim 20 , wherein:
 following transmitting of the lock signal by the transmitter, the memory control circuitry is to enter a receive mode of operation.