Interface circuit for controlling output impedance of a transmission circuit and an image sensor including the same

Abstract

An interface circuit including: a first transmission circuit outputting a first signal to a transmission line via first transfer pads; and a second transmission circuit outputting a second signal to the transmission line via second transfer pads, the first transmission circuit includes a first termination resistor block including a switch and a first termination resistor connected between the first transfer pads, the second transmission circuit includes a second termination resistor block including a switch and a second termination resistor connected between the second transfer pads, and when the first transmission circuit outputs the first signal, the second termination resistor block detects the first signal, and when the first transmission circuit is in a low-power operation mode, the second termination resistor block disconnects the second termination resistor, and when the first transmission circuit is in a high-speed data transfer mode, the second termination resistor block connects the second termination resistor.

What is claimed is: 
     
         1 . An image sensor comprising:
 a pixel array configured to generate electric charges in response to light;   a logic circuit configured to convert the electric charges into first image data; and   an interface circuit configured to transmit the first image data to an external processor via a first transmission line and a second transmission line,   wherein the interface circuit is configured to connect the first transmission line and the second transmission line when the interface circuit does not transmit the first image data to the external processor.   
     
     
         2 . The image sensor of  claim 1 , wherein the interface circuit is configured to transmit the first image data in accordance with a MIPI standard. 
     
     
         3 . The image sensor of  claim 2 , wherein the interface circuit is configured to monitor statuses of the first transmission line and the second transmission line, and
 wherein the interface circuit is configured to connect or disconnect the first transmission line and the second transmission line based on a monitoring result.   
     
     
         4 . The image sensor of  claim 2 , wherein the MIPI standard is a MIPI D-PHY. 
     
     
         5 . The image sensor of  claim 4 , wherein the interface circuit is configured to connect the first transmission line and the second transmission line when the interface circuit detects transmission of second image data, different from the first image data, via the first transmission line and the second transmission line. 
     
     
         6 . The image sensor of  claim 3 , wherein the interface circuit comprises a first resistor disposed between the first transmission line and the second transmission line, and
 wherein the first transmission line and the second transmission line are connected via the first resistor when the interface circuit does not transmit the first image data to the external processor.   
     
     
         7 . The image sensor of  claim 6 , wherein the interface circuit further comprises a first switch and a control logic, and
 wherein the control logic is configured to control the first switch to connect or disconnect the first transmission line and the second transmission line via the first resistor.   
     
     
         8 . The image sensor of  claim 7 , wherein the interface circuit further comprises a second switch and a second resistor, and
 wherein the control logic is configured to control the first switch and the second switch to connect the first transmission line and the second transmission line via the first resistor and the second resistor.   
     
     
         9 . An image sensor comprising:
 a pixel array configured to generate electric charges in response to light;   a logic circuit configured to convert the electric charges into image data; and   an interface circuit configured to transmit the image data to an external processor via a first transmission line and a second transmission line in accordance with a MIPI D-PHY,   wherein the interface circuit is configured to connect the first transmission line and the second transmission line.   
     
     
         10 . The image sensor of  claim 9 , wherein the interface circuit is configured to transmit the image data as a frame unit or a line unit of the pixel array. 
     
     
         11 . The image sensor of  claim 10 , wherein the interface circuit is configured to connect the first transmission line and the second transmission line when the interface circuit does not transmit the image data to the external processor. 
     
     
         12 . The image sensor of  claim 10 , wherein the interface circuit comprises a first switch and a first resistor, and
 wherein the first transmission line and the second transmission line are connected via the first switch and the first resistor.   
     
     
         13 . The image sensor of  claim 12 , wherein the interface circuit is configured to monitor statuses of the first transmission line and the second transmission line, and
 wherein the interface circuit is configured to connect the first transmission line and t second transmission line based on a monitoring result.   
     
     
         14 . The image sensor of  claim 12 , wherein the interface circuit further comprises a second switch and a second resistor, and
 wherein the first transmission line and the second transmission line are connected via the first switch, the first resistor, the second switch and the second resistor.   
     
     
         15 . The image sensor of  claim 14 , wherein the first switch, the first resistor, the second resistor and the second switch are sequentially connected. 
     
     
         16 . An image sensor comprising:
 a pixel array configured to generate electric charges in response to light;   a logic circuit configured to convert the electric charges into first image data; and   an interface circuit configured to transmit the first image data to an external processor via a first transmission line and a second transmission line in accordance with a MIPI D-PHY,   wherein the interface circuit is configured to adjust an impedance of the first transmission line when the interface circuit detects transmission of second image data, different from the first image data, via the first transmission line and the second transmission line.   
     
     
         17 . The image sensor of  claim 16 , wherein the interface circuit is configured to connect the first transmission line and the transmission line to adjust the impedance. 
     
     
         18 . The image sensor of  claim 17 , wherein the interface circuit is configured to connect the first transmission line to the second transmission line via a switch and a resistor.