Vector circuit with scalar operations in accelerator circuit for mathematical operations

Abstract

Embodiments of the present disclosure relate to a vector circuit in an accelerator circuit for performing vector and scalar operations. The vector circuit reads a subset of instructions from an instruction memory, each instruction including an identification of at least a portion of a first vector and an identification of at least a portion of a second vector. The vector circuit further receives a portion of input data from a data memory corresponding to the subset of instructions. The vector circuit performs a respective operation in accordance with each instruction on at least one first element of the first vector and at least one second element of the second vector to generate at least one output element of an output vector. Each instruction indicates positions in respective vectors for the at least one first element, the at least one second element and the at least one output element.

What is claimed is: 
     
         1 . An accelerator circuit comprising:
 an instruction memory storing a plurality of instructions;   a data memory storing input data; and   a vector circuit coupled to the instruction memory and the data memory, the vector circuit configured to:
 read at least a subset of the instructions from the instruction memory, each instruction in the subset of instructions including a first identification of at least a portion of a first vector and a second identification of at least a portion of a second vector, 
 receive at least a portion of the input data from the data memory that corresponds to the subset of instructions, and 
 perform a respective vector operation in accordance with each instruction in the subset on at least one first element of the first vector and at least one second element of the second vector from the received portion of input data to generate at least one output element of an output vector, each instruction in the subset indicating positions in respective vectors for (i) the at least one first element, (ii) the at least one second element, and (iii) the at least one output element. 
   
     
     
         2 . The accelerator circuit of  claim 1 , wherein each instruction in the subset indicates at least one position in the first vector for the at least one first element, at least one position in the second vector for the at least one second element, and least one position in the output vector for the at least one output element. 
     
     
         3 . The accelerator circuit of  claim 1 , wherein the vector circuit is further configured to:
 perform the respective vector operation on a first plurality of elements of the first vector and a second plurality of elements of the second vector to generate a plurality of output elements of the output vector,   wherein each instruction in the subset indicates a plurality of positions in the first vector for the first plurality of elements, a plurality of positions in the second vector for the second plurality of elements, and a plurality of positions in the output vector for the plurality of output elements.   
     
     
         4 . The accelerator circuit of  claim 1 , wherein the vector circuit is further configured to:
 perform the respective vector operation on a first plurality of elements of the first vector and a second element of the second vector to generate a plurality of output elements of the output vector,   wherein each instruction in the subset indicates a plurality of positions in the first vector for the first plurality of elements, a position in the second vector for the second element, and a plurality of positions in the output vector for the plurality of output elements.   
     
     
         5 . The accelerator circuit of  claim 1 , wherein the vector circuit is further configured to:
 perform the respective vector operation on a first element of the first vector and a second element of the second vector to generate an output element of the output vector,   wherein each instruction in the subset indicates a position in the first vector for the first element, a position in the second vector for the second element, and a position in the output vector for the output element.   
     
     
         6 . The accelerator circuit of  claim 1 , wherein the vector circuit is further configured to receive the at least one first element and the at least one second element from the data memory at a vector register file of the vector circuit in accordance with each instruction in the subset. 
     
     
         7 . The accelerator circuit of  claim 6 , wherein the vector circuit is further configured to store the least one output element in the vector register file in accordance with each instruction in the subset for further use by the vector circuit. 
     
     
         8 . The accelerator circuit of  claim 6 , further comprising a buffer circuit coupled to the data memory, and the vector circuit is further configured to store the least one output element in the buffer circuit in accordance with each instruction in the subset. 
     
     
         9 . The accelerator circuit of  claim 7 , further comprising a load and store circuit including the buffer circuit, the load and store circuit configured to store the least one output element from the buffer circuit in the data memory. 
     
     
         10 . The accelerator circuit of  claim 1 , wherein the accelerator circuit is integrated into an image signal processor circuit or a neural processor circuit. 
     
     
         11 . A method of operating an accelerator circuit, comprising:
 storing a plurality of instructions in an instruction memory of the accelerator circuit;   reading at least a subset of the instructions from the instruction memory by a vector circuit of the accelerator circuit coupled to the instruction memory, each instruction in the subset of instructions including a first identification of at least a portion of a first vector and a second identification of at least a portion of a second vector;   receiving, at the vector circuit, at least a portion of the input data from a data memory of the accelerator circuit, the portion of input data corresponds to the subset of instructions; and   performing, by the vector circuit, a respective vector operation in accordance with each instruction in the subset on at least one first element of the first vector and at least one second element of the second vector from the received portion of input data to generate at least one output element of an output vector, each instruction in the subset indicating positions in respective vectors for (i) the at least one first element, (ii) the at least one second element, and (iii) the at least one output element.   
     
     
         12 . The method of  claim 11 , wherein each instruction in the subset indicates at least one position in the first vector for the at least one first element, at least one position in the second vector for the at least one second element, and least one position in the output vector for the at least one output element. 
     
     
         13 . The method of  claim 11 , further comprising:
 performing, by the vector circuit, the respective vector operation on a first plurality of elements of the first vector and a second plurality of elements of the second vector to generate a plurality of output elements of the output vector,   wherein each instruction in the subset indicates a plurality of positions in the first vector for the first plurality of elements, a plurality of positions in the second vector for the second plurality of elements, and a plurality of positions in the output vector for the plurality of output elements.   
     
     
         14 . The method of  claim 11 , further comprising:
 performing, by the vector circuit, the respective vector operation on a first plurality of elements of the first vector and a second element of the second vector to generate a plurality of output elements of the output vector,   wherein each instruction in the subset indicates a plurality of positions in the first vector for the first plurality of elements, a position in the second vector for the second element, and a plurality of positions in the output vector for the plurality of output elements.   
     
     
         15 . The method of  claim 11 , further comprising:
 performing, by the vector circuit, the respective vector operation on a first element of the first vector and a second element of the second vector to generate an output element of the output vector,   wherein each instruction in the subset indicates a position in the first vector for the first element, a position in the second vector for the second element, and a position in the output vector for the output element.   
     
     
         16 . The method of  claim 10 , further comprising:
 receiving the at least one first element and the at least one second element from the data memory at a vector register file of the vector circuit in accordance with each instruction in the subset.   
     
     
         17 . The method of  claim 16 , further comprising:
 storing the least one output element into the vector register file in accordance with each instruction in the subset for further use by the vector circuit.   
     
     
         18 . An electronic device, comprising:
 a system memory storing input data; and   an accelerator circuit coupled to the system memory, the accelerator circuit including:
 a data memory configured to receive and store the input data from the system memory, 
 an instruction memory storing a plurality of instructions, and 
 a vector circuit coupled to the instruction memory and the data memory, the vector circuit configured to:
 read at least a subset of the instructions from the instruction memory, each instruction in the subset of instructions including a first identification of at least a portion of a first vector and a second identification of at least a portion of a second vector, 
 receive at least a portion of the input data from the data memory that corresponds to the subset of instructions, and 
 perform a respective vector operation in accordance with each instruction in the subset on at least one first element of the first vector and at least one second element of the second vector from the received portion of input data to generate at least one output element of an output vector, each instruction in the subset indicating positions in respective vectors for (i) the at least one first element, (ii) the at least one second element, and (iii) the at least one output element. 
 
   
     
     
         19 . The electronic device of  claim 18 , wherein each instruction in the subset indicates at least one position in the first vector for the at least one first element, at least one position in the second vector for the at least one second element, and least one position in the output vector for the at least one output element. 
     
     
         20 . The electronic device of  claim 18 , wherein the vector circuit is further configured to:
 perform the respective vector operation on a first plurality of elements of the first vector and a second element of the second vector to generate a plurality of output elements of the output vector,   wherein each instruction in the subset indicates a plurality of positions in the first vector for the first plurality of elements, a position in the second vector for the second element, and a plurality of positions in the output vector for the plurality of output elements.