Distributed temporal cache for systems on a chip

Abstract

A system and method for accessing cache lines of an N-way set associative cache distributed across local memory of compute elements. The set associative cache includes a plurality of sets, with each location in cacheable local memory mapped to one of the sets and each set including N locations for caching data blocks read from the cacheable memory. Each set is mapped to one of the local memories, when that local memory is not in use by local compute elements. A cache controller is configured to receive a read request, to identify a data block in the cacheable memory associated with the address, to determine if the identified data block is in cache in one of the local memories, and, if the identified data block is in cache in one of the local memories, to fetch the identified data block from the cache.

What is claimed is: 
     
         1 . A system on a chip (SoC) comprising:
 a plurality of local memories, including a first local memory and a second local memory;   a cache memory distributed among the plurality of local memories;   a first subsystem comprising a first compute element and the first local memory, the first compute element connected to the first local memory;   a second subsystem comprising a second compute element and the second local memory, the second compute element connected to the second local memory; and   a cache controller,   wherein the first compute element is configured to access the cache memory stored in the second local memory via the cache controller.   
     
     
         2 . The SoC of  claim 1 , further comprising:
 a third subsystem comprising a third compute element and a third local memory, the third compute element connected to the third local memory, wherein the plurality of local memories further include the third local memory,   wherein the first compute element is configured to access the cache memory stored in the third local memory via the cache controller.   
     
     
         3 . The SoC of  claim 1 , wherein the first subsystem, the second subsystem, and the cache controller are connected via a network-on-chip (NoC). 
     
     
         4 . The SoC of  claim 1 , wherein the cache controller is an N-way set associative cache controller. 
     
     
         5 . The SoC of  claim 1 , wherein the cache controller is configured to:
 receive a first read request having an address; and   determine if a data block associated with the address is in a cache in one of the plurality of local memories.   
     
     
         6 . The SoC of  claim 5 ,
 wherein the address includes a set number, and   wherein the cache controller is configured to determine a location, associated with the set number, where a cache line is stored.   
     
     
         7 . The SoC of  claim 6 , wherein the cache controller is further configured to:
 in response to a determination the data block associated with the address is in a cache in one of the plurality of local memories, fetch the data block from the cache.   
     
     
         8 . The SoC of  claim 6 , the first subsystem further comprising a first cache memory manager and a first local memory controller,
 wherein in response to the determination that the data block associated with the address is in a cache in one of the plurality of local memories, the cache controller is configured to issue a second read request to the first cache memory manager requesting the first cache memory manager fetch data from the cache line,   the first cache memory manager is configured to forward the second read request to the first local memory controller, and   in response to receiving the second read request, the first local memory controller is configured to fetch the data from the cache line and forward the data to the first cache memory manager.   
     
     
         9 . The SoC of  claim 8 , wherein the first cache memory manager is configured to return the data to an initiator of the read request and to the cache controller to terminate the request in the cache controller,
 wherein the cache controller is configured to issue a read request to the first cache memory manager of the first subsystem requesting data from a cache line associated with the read request.   
     
     
         10 . A system on a chip (SoC) comprising:
 a plurality of local memories, including a first local memory;   a first subsystem comprising a first compute element and the first local memory, the first compute element connected to the first local memory; and   an N-way set associative cache controller, the N-way set associative cache controller configured to control an N-way set associative cache having a plurality of sets, wherein each location in a cacheable memory accessible to the SoC is mapped to one of the sets, wherein each set includes N locations for caching data blocks read from the cacheable memory, wherein N is an integer greater than one.   
     
     
         11 . The SoC of  claim 10 , further comprising a second subsystem comprising a second compute element and a second local memory, the second compute element connected to the second local memory, the plurality of local memories further includes the second local memory. 
     
     
         12 . The SoC of  claim 11 , wherein, when the first compute element is executing an application in the first local memory, the set associative cache is further configured to disable, from caching, sets of the cache mapped to the first local memory, and
 wherein, when the second compute element is executing an application in the second local memory, the set associative cache is further configured to disable, from caching, sets of the cache mapped to the second local memory.   
     
     
         13 . The SoC of  claim 10 , wherein a mapped set of the mapped sets is determined as being available for caching when a corresponding mapped local memory, of the plurality of local memories, is determined as being available for caching. 
     
     
         14 . The SoC of  claim 10 , wherein the plurality of memories are addressable as shared memory. 
     
     
         15 . The SoC of  claim 10 , wherein the local memories are Static Random-Access Memory (SRAM). 
     
     
         16 . The SoC of  claim 10 , wherein sets from the N-way set associative cache are mapped to one or more of the plurality of local memories when the respective local memories are not being used by local compute elements. 
     
     
         17 . The SoC of  claim 10 , wherein the N-way set associative cache controller is configured to receive a read request having an address, to identify a data block in the cacheable memory associated with the address, to determine the identified data block is in a cache in one of the plurality of local memories, and, in response to the determination that the identified data block is in a cache in one of the plurality of local memories, fetch the identified data block from the cache. 
     
     
         18 . The SoC of  claim 10 , wherein the N-way set associative cache controller is configured to receive a read request having an address, to identify a data block in the cacheable memory associated with the address, to determine the identified data block is not in a cache in one of the plurality of local memories, and in response to the determination that the identified data block is not in a cache in one of the plurality of local memories, fetch the identified data block from the cacheable memory. 
     
     
         19 . The SoC of  claim 17 , wherein the address includes a tag, and
 wherein the N-way set associative cache controller is configured to determine whether the identified data block is in a cache in one of the plurality of local memories based on the tag.   
     
     
         20 . In a system on a chip (SoC) having on-chip memory, cacheable memory and a cache controller having a plurality of sets, wherein the on-chip memory includes local memory distributed among a plurality of subsystems, a method of caching data from the cacheable memory in the local memory, the method comprising:
 receiving a read request from a processor, the read request having an address;   determining data associated with the address is stored in the distributed local memory;   in response to determining that the data associated with the address is stored in a cache in the local memory, reading data from the cache in the local memory based on the address in the read request and forwarding the data to the processor.