Memory system and information processing system having an address translation table and a data map updated based on an invalidation request having a fragment table

Abstract

According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory is configured to store an address translation table and a data map. In a case where an invalidation command for invalidating the data written in the non-volatile memory is received from the host, the controller is configured to update the address translation table and the data map based on the invalidation command. A response to the invalidation command is transmitted to the host after the address translation table is updated and before the data map is updated.

What is claimed is: 
     
         1 . A memory system that is connectable to a host, comprising:
 a non-volatile memory; and   a controller configured to be electrically connected to the non-volatile memory to control the non-volatile memory,   wherein the non-volatile memory is configured to store
 an address translation table for managing a correspondence between a logical address used by the host to access the memory system and a physical address in which data in the non-volatile memory is written, and 
 a data map including first information, 
   the first information includes information indicating whether the data written in each of continuous physical addresses of the non-volatile memory is valid or invalid,   in a case where an invalidation command for invalidating the data written in the non-volatile memory is received from the host, the controller is configured to update the address translation table and the data map based on the invalidation command, and   a response to the invalidation command is transmitted to the host after the address translation table is updated and before the data map is updated.   
     
     
         2 . The memory system according to  claim 1 , wherein in a case where a command other than the invalidation command is received from the host after the invalidation command, the command is executed after the response to the invalidation command is transmitted to the host. 
     
     
         3 . The memory system according to  claim 2 ,
 wherein the invalidation command comprises a logical address for accessing data to be invalidated by the invalidation command, and   the other command comprises at least one of a write command, a read command, and an invalidation command other than the invalidation command, the other command designating a logical address in the invalidation command.   
     
     
         4 . The memory system according to  claim 1 , wherein the controller is configured to store an invalidation request based on the invalidation command in a queue, retrieve the invalidation request from the queue after the response to the invalidation command is transmitted to the host, and update the data map based on the invalidation request. 
     
     
         5 . The memory system according to  claim 4 ,
 wherein the address translation table comprises a plurality of fragment tables,   a range of logical address is allocated to each of the fragment tables,   the invalidation command comprises a logical address for accessing data to be invalidated by the invalidation command,   the controller is configured to update the fragment table specified based on the logical address in the invalidation command among the fragment tables, and   the invalidation request comprises a fragment table before being updated.   
     
     
         6 . The memory system according to  claim 5 , wherein discrimination information for discriminating data to be invalidated by the invalidation command is given to the fragment table in the invalidation request. 
     
     
         7 . The memory system according to  claim 6 ,
 wherein the discrimination information comprises a magic number, and   the magic number is set in the fragment table in the invalidation request.   
     
     
         8 . The memory system according to  claim 6 , wherein the discrimination information comprises a range of logical addresses in the invalidation command. 
     
     
         9 . The memory system according to  claim 4 , wherein the invalidation request is stored in the queue at the same time as transmission of a response to the invalidation command or after the transmission. 
     
     
         10 . The memory system according to  claim 4 ,
 wherein other commands received from the host after the invalidation command are executed in preference to the invalidation request, and   the controller is configured to retrieve the invalidation request from the queue after the other commands are executed and update the data map based on the invalidation request.   
     
     
         11 . The memory system according to  claim 5 ,
 wherein other commands received from the host after the invalidation command are executed in preference to the invalidation request, and   the controller is configured to retrieve the invalidation request from the queue after the other commands are executed and update the data map based on the invalidation request.   
     
     
         12 . The memory system according to  claim 1 , wherein the address translation table has a hierarchical structure and comprises a plurality of fragment tables corresponding to a plurality of hierarchies. 
     
     
         13 . The memory system according to  claim 4 , wherein the address translation table has a hierarchical structure and comprises a plurality of fragment tables corresponding to a plurality of hierarchies. 
     
     
         14 . The memory system according to  claim 5 , wherein the address translation table has a hierarchical structure and comprises a plurality of fragment tables corresponding to a plurality of hierarchies. 
     
     
         15 . The memory system according to  claim 10 , wherein the address translation table has a hierarchical structure and comprises a plurality of fragment tables corresponding to a plurality of hierarchies. 
     
     
         16 . The memory system according to  claim 11 , wherein the address translation table has a hierarchical structure and comprises a plurality of fragment tables corresponding to a plurality of hierarchies. 
     
     
         17 . The memory system according to  claim 4 , wherein the controller is configured to store a plurality of invalidation requests based on a plurality of invalidation commands in a queue, and execute priority control for the invalidation requests. 
     
     
         18 . The memory system according to  claim 17 , wherein the controller is configured to preferentially update the data map based on the invalidation request comprising the fragment table whose hierarchy is higher than the hierarchy corresponding to the fragment table in each of the invalidation requests. 
     
     
         19 . The memory system according to  claim 17 , wherein the controller is configured to preferentially update the data map based on an invalidation request designated by a dedicated command. 
     
     
         20 . The memory system according to  claim 1 , wherein the data map includes second information indicating the first physical address of the continuous physical addresses.