Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<θ1<115° measured from the upper surface of the erase gate.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a plurality of stacked structures arranged along a first direction disposed over a semiconductor substrate,   wherein the plurality of stacked structures are spaced-apart from each other and extend in a second direction perpendicular to the first direction, and   each stacked structure includes:   a first conductive layer disposed over a semiconductor substrate;   a first dielectric layer disposed over the first conductive layer; and   a second conductive layer disposed over the first dielectric layer,   wherein the first conductive layer, first dielectric layer, and second conductive layer are arranged in order along a third direction perpendicular to the first and second directions;   first sidewall spacers disposed on opposing sides of each of the second conductive layers and an upper surface of each of the first conductive layers;   second sidewall spacers disposed on opposing sides of the first sidewall spacers and opposing sides of each of the first conductive layers,   wherein the first sidewall spacers have a three layer structure including an inner layer, a middle layer, and an outer layer, wherein the middle layer is formed of a different material than the inner layer and the outer layer;   a third conductive layer disposed over the semiconductor substrate between adjacent stacked structures;   a fourth conductive layer disposed over the second sidewall spacers on opposing sides of each of the stacked structures from where the third conductive layer is disposed; and   an insulating layer disposed over the second conductive layer.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the insulating layer has a three layer structure including at least one silicon nitride layer and at least one silicon oxide layer. 
     
     
         3 . The semiconductor device of  claim 1 , wherein an upper surface of the third conductive layer is located higher than an upper surface of the second conductive layer with respect to the substrate. 
     
     
         4 . The semiconductor device of  claim 1 , further comprising a second dielectric layer disposed between the first conductive layer and the substrate. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the first dielectric layer comprises a silicon oxide layer, a silicon nitride layer, or multilayers of silicon oxide and silicon nitride. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising a silicon oxide layer disposed between the first conductive layer and the substrate. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the inner layer and the outer layer of the first sidewall spacers are silicon oxide layers. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the inner layer and the outer layer of the first sidewall spacers are silicon nitride layers. 
     
     
         9 . A semiconductor device, comprising:
 a first stacked structure and a second stacked structure arranged along a first direction disposed over a semiconductor substrate,   wherein the first stacked structure and the second stacked structure are spaced-apart from each other and extend in a second direction perpendicular to the first direction, and   each stacked structure includes:   a first conductive layer disposed over a semiconductor substrate;   a first dielectric layer disposed over the first conductive layer; and   a second conductive layer disposed over the first dielectric layer,   wherein the first conductive layer, first dielectric layer, and second conductive layer are arranged in order along a third direction perpendicular to the first and second directions, and   wherein the first conductive layer has a greater width along the first direction than the second conductive layer;   first sidewall spacers disposed on opposing sides of each of the second conductive layers;   second sidewall spacers disposed on opposing sides of the first sidewall spacers and opposing sides of each of the first conductive layers,   wherein the first sidewall spacers have a three layer structure including at least one nitride layer and at least one oxide layer;   a third conductive layer disposed over the semiconductor substrate between the first stacked structure and the second stacked structure;   a fourth conductive layer disposed over the second sidewall spacers on opposing sides of each of the stacked structures from where the third conductive layer is disposed; and   an insulating layer disposed over the second conductive layer,   wherein the insulating layer has a two layer structure including a nitride layer and an oxide layer.   
     
     
         10 . The semiconductor device of  claim 9 , wherein an upper surface of the third conductive layer is located higher than an upper surface of the second conductive layer with respect to the substrate. 
     
     
         11 . The semiconductor device of  claim 9 , further comprising a second dielectric layer disposed between the first conductive layer and the substrate. 
     
     
         12 . The semiconductor device of  claim 9 , wherein the first dielectric layer comprises a silicon oxide layer, a silicon nitride layer, or multilayers of silicon oxide and silicon nitride. 
     
     
         13 . The semiconductor device of  claim 9 , wherein the first sidewall spacers have an inner layer, a middle layer, and an outer layer; and the inner layer and the outer layer are silicon nitride layers. 
     
     
         14 . The semiconductor device of  claim 9 , wherein the first sidewall spacers have an inner layer, a middle layer, and an outer layer; and the inner layer and the outer layer are silicon oxide layers. 
     
     
         15 . The semiconductor device of  claim 9 , wherein the second sidewall spacers comprise silicon oxide. 
     
     
         16 . A method for manufacturing a semiconductor device, comprising:
 forming a first conductive layer over a substrate;   forming a first dielectric layer over the first conductive layer;   forming a second conductive layer over the first dielectric layer;   forming an insulating layer over the second conductive layer;   selectively etching the insulating layer, second conductive layer, and the first dielectric layer to form a first stacked structure and a second stacked structure spaced-apart from the first structure arranged along a first direction,   forming first sidewall spacers on opposing sides of each of the first stacked structure and the second stacked structure;   etching exposed portions of the first conductive layer to form remaining portions of the first conductive layer underlying the first sidewall spacers and the first dielectric layer in each of the first stacked structure and the second stacked structure,   wherein the remaining portions of the first conductive layer are wider than remaining portions of the second conductive layer in each stacked structure;   forming second sidewall spacers over the first sidewall spacers and opposing sides of the first conductive layer;   forming a third conductive layer over the second sidewall spacers, insulating layer, and between each stacked structure; and   etching the third conductive layer so that a first remaining portion of the third conductive layer between the first stacked structure is isolated from second remaining portions of the third conductive layer on opposing sides of each stacked structure.   
     
     
         17 . The method according to  claim 16 , wherein the first sidewall spacer includes a three layer structure including at least one silicon nitride layer and at least one silicon oxide layer. 
     
     
         18 . The method according to  claim 16 , wherein the insulating layer includes a three layer structure including at least one silicon nitride layer and at least one silicon oxide layer. 
     
     
         19 . The method according to  claim 16 , wherein the first dielectric layer comprises a silicon oxide layer, a silicon nitride layer, or multilayers of silicon oxide and silicon nitride. 
     
     
         20 . The method according to  claim 16 , further comprising forming a hard mask layer over the second conductive layer before selectively etching the insulating layer, second conductive layer, and the first dielectric layer.