Semiconductor memory device

Abstract

A semiconductor memory device includes a substrate, and a capacitor structure on the substrate and including a lower electrode, a capacitor dielectric layer, and an upper electrode, wherein the capacitor dielectric layer includes a lower interface layer on the lower electrode and doped with impurities of a first conductive type, an upper interface layer beneath the upper electrode and doped with impurities of a second conductive type other than the first conductive type, and a dielectric structure between the lower interface layer and the upper interface layer.

What is claimed is: 
     
         1 . A semiconductor memory device, comprising:
 a substrate; and   a capacitor structure on the substrate, the capacitor structure including a lower electrode, a capacitor dielectric layer, and an upper electrode,   wherein the capacitor dielectric layer includes:
 a lower interface layer on the lower electrode and doped with impurities of a first conductive type; 
 an upper interface layer beneath the upper electrode and doped with impurities of a second conductive type other than the first conductive type; and 
 a dielectric structure between the lower interface layer and the upper interface layer. 
   
     
     
         2 . The semiconductor memory device as claimed in  claim 1 , wherein the first conductive type is n type, and the second conductive type is p type. 
     
     
         3 . The semiconductor memory device as claimed in  claim 1 , wherein each of the lower interface layer and the upper interface layer includes a metal oxide, and the impurities of the first conductive type and the impurities of the second conductive type are atom ions. 
     
     
         4 . The semiconductor memory device as claimed in  claim 3 , wherein a percentage of the impurities of the first conductive type among metal atoms included in the lower interface layer is less than 5 atomic %, and a percentage of the impurities of the second conductive type among metal atoms included in the upper interface layer is less than 5 atomic %. 
     
     
         5 . The semiconductor memory device as claimed in  claim 3 , wherein a percentage of the impurities of the first conductive type among metal atoms included in the lower interface layer is greater than a percentage of the impurities of the second conductive type among metal atoms included in the upper interface layer. 
     
     
         6 . The semiconductor memory device as claimed in  claim 1 , wherein a thickness of the lower interface layer is greater than a thickness of the upper interface layer. 
     
     
         7 . The semiconductor memory device as claimed in  claim 1 , wherein the dielectric structure has a stack structure including a lower dielectric layer, an upper dielectric layer, and an insertion layer between the lower dielectric layer and the upper dielectric layer, and a bandgap of the insertion layer is greater than a bandgap of each of the lower dielectric layer and the upper dielectric layer. 
     
     
         8 . The semiconductor memory device as claimed in  claim 7 , wherein a dielectric constant of the upper dielectric layer is greater than a dielectric constant of the lower dielectric layer. 
     
     
         9 . The semiconductor memory device as claimed in  claim 7 , wherein a thickness of the upper dielectric layer is greater than a thickness of the lower dielectric layer. 
     
     
         10 . The semiconductor memory device as claimed in  claim 7 , wherein a thickness of the insertion layer is less than a thickness of each of the lower interface layer and the upper interface layer. 
     
     
         11 . A semiconductor memory device, comprising:
 a substrate having a memory cell region; and   capacitor structures in the memory cell region of the substrate, the capacitor structures including lower electrodes, an upper electrode, and a capacitor dielectric layer between the lower electrodes and the upper electrode,   wherein the capacitor dielectric layer includes:
 a lower interface layer doped with impurities of a first conductive type, a lower dielectric layer, an insertion layer, an upper dielectric layer, and an upper interface layer doped with impurities of a second conductive type other than the first conductive type, which are sequentially stacked on the lower electrode, and a bandgap of the insertion layer is greater than each of a bandgap of the lower dielectric layer and a bandgap of the upper dielectric layer. 
   
     
     
         12 . The semiconductor memory device as claimed in  claim 11 , wherein each of the lower interface layer and the upper interface layer includes metal oxide, the impurities of the first conductive type and the impurities of the second conductive type are atom ions, and each of a percentage of the impurities of the first conductive type among metal atoms included in the lower interface layer and a percentage of the impurities of the second conductive type among metal atoms included in the upper interface layer is less than 5 atomic %. 
     
     
         13 . The semiconductor memory device as claimed in  claim 11 , wherein a thickness of the lower interface layer is greater than or equal to a thickness of the upper interface layer. 
     
     
         14 . The semiconductor memory device as claimed in  claim 11 , wherein a thickness of the lower interface layer is less than a thickness of the upper interface layer. 
     
     
         15 . The semiconductor memory device as claimed in  claim 11 , wherein a thickness of each of the lower interface layer and the upper interface layer is about 10 Å or less, and a thickness of the insertion layer is about 5 Å or less. 
     
     
         16 . The semiconductor memory device as claimed in  claim 11 , wherein the capacitor dielectric layer includes a material having an antiferroelectricity characteristic, a material having a ferroelectricity characteristic, or a material in which the antiferroelectricity characteristic is combined with the ferroelectricity characteristic. 
     
     
         17 . The semiconductor memory device as claimed in  claim 11 , wherein the upper dielectric layer has a dielectric constant greater than a dielectric constant of the lower dielectric layer and has a thickness greater than a thickness of the lower dielectric layer. 
     
     
         18 . A semiconductor memory device, comprising:
 a substrate having active regions in a memory cell region;   buried contacts connected to the active regions;   landing pads on the buried contacts; and   capacitor structures in the memory cell region of the substrate and including lower electrodes electrically connected to the landing pads, an upper electrode, and a capacitor dielectric layer between the lower electrodes and the upper electrode,   wherein the capacitor dielectric layer includes a lower interface layer that is a metal oxide doped with n-type impurities that are metal atoms, a lower dielectric layer, an insertion layer, an upper dielectric layer, and an upper interface layer that is a metal oxide doped with p-type impurities that are metal atoms, which are sequentially stacked on the lower electrode, a thickness of the lower interface layer being greater than a thickness of the upper interface layer, and a thickness of the insertion layer being less than the thickness of the upper interface layer.   
     
     
         19 . The semiconductor memory device as claimed in  claim 18 , wherein a bandgap of the insertion layer is greater than each of a bandgap of the lower dielectric layer and a bandgap of the upper dielectric layer, and a thickness of the upper dielectric layer is greater than a thickness of the lower dielectric layer. 
     
     
         20 . The semiconductor memory device as claimed in  claim 18 , wherein a thickness of the capacitor dielectric layer is about 30 Å to about 60 Å, the thickness of the lower interface layer is about 10 Å or less, the thickness of the upper interface layer is about 7 Å or less, and the thickness of the insertion layer is about 5 Å or less.