Manufacturing method for high-voltage transistor

Abstract

The disclosure discloses a manufacturing method for high-voltage transistor. The manufacturing method comprises: providing a substrate; forming a recess in the substrate; forming an epitaxial doped structure with a first conductivity type in the recess of the substrate, wherein a top portion of the epitaxial doped structure comprises a top undoped epitaxial layer; forming a gate structure on the substrate and at least overlapping with the top undoped epitaxial layer; and forming a source/drain region with a second conductivity type in the epitaxial doped structure on a side of the gate structure. The first conductivity type is different from the second conductivity type.

What is claimed is: 
     
         1 . A manufacturing method for high-voltage transistor, comprising:
 providing a substrate;   forming a recess in the substrate;   forming an epitaxial doped structure with a first conductivity type in the recess of the substrate, wherein a top portion of the epitaxial doped structure comprises a top undoped epitaxial layer;   forming a gate structure on the substrate and at least overlapping with the top undoped epitaxial layer; and   forming a source/drain region with a second conductivity type in the epitaxial doped structure on a side of the gate structure,   wherein the first conductivity type is different from the second conductivity type.   
     
     
         2 . The manufacturing method for high-voltage transistor according to  claim 1 , wherein the formed epitaxial doped structure comprises a plurality of doped epitaxial layers located under the top undoped epitaxial layer, and a doping concentration of the first conductivity type decreases in a gradient manner. 
     
     
         3 . The manufacturing method for high-voltage transistor according to  claim 2 , wherein the formed epitaxial doped structure comprises a bottom undoped epitaxial layer, which is interfaced with the substrate. 
     
     
         4 . The manufacturing method for high-voltage transistor according to  claim 2 , wherein the provided substrate is a silicon substrate, and the formed epitaxial doped structure comprises a plurality of silicon epitaxial layers,
 wherein a top silicon epitaxial layer is the top undoped epitaxial layer, a bottom silicon epitaxial layer is a bottom undoped epitaxial layer, and a part of the plurality of silicon epitaxial layers is between the top undoped epitaxial layer and the bottom undoped epitaxial layer and serves as the doped epitaxial layer.   
     
     
         5 . The manufacturing method for high-voltage transistor according to  claim 2 , wherein the first conductive layer is of N conductivity type or P conductivity type, and the plurality of doped epitaxial layers are respectively and correspondingly doped with a N conductivity type dopant or a P conductivity type dopant. 
     
     
         6 . The manufacturing method for high-voltage transistor according to  claim 5 , wherein the plurality of doped epitaxial layers comprise SiP with N-conductivity type or SiGe with P-conductivity type. 
     
     
         7 . The manufacturing method for high-voltage transistor according to  claim 1 , wherein the formed gate structure comprises:
 a high-voltage gate insulating layer disposed on the substrate;   a gate layer disposed on the high-voltage gate insulating layer; and   a spacer wall disposed on the substrate and located on a side wall of the gate layer,   wherein the top undoped epitaxial layer is located under the spacer wall and extends below the high-voltage gate insulating layer.   
     
     
         8 . The manufacturing method for high-voltage transistor according to  claim 1 , wherein the step of forming the epitaxial doped structure comprises an in-situ doping process to form a plurality of doped epitaxial layers.