Execution of computation graphs

Abstract

A computation graph is accessed. In the computation graph, operations to be performed are represented as interior nodes, inputs to the operations are represented as leaf nodes, and a result of the operations is represented as a root. Selected sets of the operations are combined to form respective kernels of operations. Code is generated execute the kernels of operations. The code is executed to determine the result.

What is claimed is: 
     
         1 . A processor, comprising:
 one or more circuits to cause two or more computational graph nodes to be combined to generate two or more different software kernels.   
     
     
         2 . The processor of  claim 1 , wherein the two or more different software kernels are to include two or more different sets of operations, the two or more different sets of operations represented by the two or more computational graph nodes to be combined. 
     
     
         3 . The processor of  claim 1 , wherein the two or more different software kernels are to include operations to be performed together. 
     
     
         4 . The processor of  claim 1 , wherein the two or more different software kernels are to include operations to be performed on different processing architectures. 
     
     
         5 . The processor of  claim 1 , wherein the one or more circuits are further to identify the two or more computational graph nodes based, at least in part, on traversing a computation graph until a first object is reached that is to be materialized as an input of a second object. 
     
     
         6 . The processor of  claim 1 , wherein the two or more different software kernels are to include a first software kernel and a second software kernel, and
 wherein the second software kernel is to be dependent on the first software kernel.   
     
     
         7 . The processor of  claim 1 , wherein the one or more circuits are further to store one or more results of one or more first operations performed on the two or more different software kernels to be input into one or more second operations. 
     
     
         8 . A system, comprising memory to store executable instructions that, if executed by one or more processors, cause the system to combine two or more computational graph nodes to generate two or more different software kernels. 
     
     
         9 . The system of  claim 8 , wherein the two or more different software kernels are to include two or more different phases of operations, the two or more different phases of operations represented by the two or more computational graph nodes to be combined. 
     
     
         10 . The system of  claim 8 , wherein each software kernel of the two or more different software kernels is to include operations to be performed together. 
     
     
         11 . The system of  claim 8 , wherein the two or more different software kernels are to include two or more sequences of operations to be performed on different processing architectures. 
     
     
         12 . The system of  claim 8 , wherein the memory stores further executable instructions that, if executed by the one or more processors, cause the system to identify the two or more computational graph nodes based, at least in part, on traversing a computation graph until a first data structure is reached that is to be materialized as an input of a second data structure. 
     
     
         13 . The system of  claim 8 , wherein the two or more different software kernels are to include a first software kernel and a second software kernel, and
 wherein the second software kernel is to be dependent on an output of the firsts software kernel.   
     
     
         14 . The system of  claim 8 , further comprising a register,
 wherein the memory stores further executable instructions that, if executed by the one or more processors, cause the system to store, in the register, one or more results of one or more first operations performed on the two or more different software kernels to be input into one or more second operations.   
     
     
         15 . A method, comprising:
 combining two or more computational graph nodes to generate two or more different software kernels.   
     
     
         16 . The method of  claim 15 , wherein the two or more different software kernels are to include sequential phases of operations, the sequential phases of operations represented by the two or more computational graph nodes to be combined. 
     
     
         17 . The method of  claim 15 , wherein each software kernel of the two or more different software kernels is to include operations to be performed in parallel. 
     
     
         18 . The method of  claim 15 , wherein the two or more different software kernels are to perform two or more sets of operations on two or more processing architectures, and
 wherein each software kernel of the two or more different software kernels is to include a set of operations of the two or more sets of operations to be performed on a processing architecture of the two or more processing architectures.   
     
     
         19 . The method of  claim 15 , further comprising identifying the two or more computational graph nodes based, at least in part, on traversing a computation graph until a first data structure is reached that is to be materialized as an input of a second data structure,
 wherein the two or more different software kernels are to include a first software kernel and a second software kernel, and   wherein the first software kernel is to provide the input to the second software kernel.   
     
     
         20 . The method of  claim 15 , further comprising storing one or more results of one or more first operations performed on a first set of software kernels of the two or more different software kernels to be input into one or more second operations to be performed on a second set of software kernels of the two or more different software kernels.