Non-volatile memory device

Abstract

In some embodiments, a non-volatile memory device includes a first semiconductor layer that includes a first memory cell array disposed on a first cell region, a second memory cell array disposed on a second cell region, and a first metal pad. The non-volatile memory device further includes a second semiconductor layer that includes a first peripheral circuit disposed on a first region and coupled to the first memory cell array, a second peripheral circuit disposed on a second region and coupled to the second memory cell array, and a second metal pad. The first region includes a first peripheral circuit region that overlaps the first cell region in the vertical direction, and a second peripheral circuit region that does not overlap the first cell region in the vertical direction, and the second region overlaps the second cell region in the vertical direction.

1 . A non-volatile memory device, comprising:
 a first semiconductor layer that includes:
 a first memory cell array that is disposed on a first cell region of the first semiconductor layer, wherein the first memory cell array includes a first plurality of word lines stacked in a vertical direction and a first plurality of memory cells respectively coupled to the first plurality of word lines; 
 a second memory cell array that is disposed on a second cell region of the first semiconductor layer, wherein the second memory cell array includes a second plurality of word lines stacked in the vertical direction and a second plurality of memory cells respectively coupled to the second plurality of word lines; and 
 a first metal pad; and 
   a second semiconductor layer that includes:
 a first peripheral circuit disposed on a first region of the second semiconductor layer and coupled to the first memory cell array; 
 a second peripheral circuit disposed on a second region of the second semiconductor layer and coupled to the second memory cell array; and 
 a second metal pad, 
   wherein the second semiconductor layer is coupled, in the vertical direction, to the first semiconductor layer by the first metal pad and the second metal pad in a bonding manner,   wherein the first region includes a first peripheral circuit region that overlaps the first cell region in the vertical direction, and a second peripheral circuit region that does not overlap the first cell region in the vertical direction, and   wherein the second region overlaps the second cell region in the vertical direction.   
     
     
         2 . The non-volatile memory device of  claim 1 , wherein the first peripheral circuit includes a first page buffer circuit,
 wherein a portion of the first page buffer circuit is disposed on the first peripheral circuit region,   wherein another portion of the first page buffer circuit is disposed on the second peripheral circuit region,   wherein the second peripheral circuit includes a second page buffer circuit, and   wherein the second page buffer circuit is disposed on the second region.   
     
     
         3 . The non-volatile memory device of  claim 2 , wherein the first page buffer circuit includes a sensing latch and a cache latch,
 wherein the sensing latch is disposed on the first peripheral circuit region, and   wherein the cache latch is disposed on the second peripheral circuit region.   
     
     
         4 . The non-volatile memory device of  claim 3 , wherein the first page buffer circuit further includes a force latch, an upper-bit latch, and a lower-bit latch, and
 wherein the force latch, the upper-bit latch, and the lower-bit latch are disposed on the first peripheral circuit region.   
     
     
         5 . The non-volatile memory device of  claim 3 , wherein the first page buffer circuit further includes a high-voltage transistor coupled to one of a plurality of bit lines, and
 wherein the high-voltage transistor is disposed on the first peripheral circuit region.   
     
     
         6 . The non-volatile memory device of  claim 2 , wherein the first page buffer circuit includes a sensing latch, a cache latch, and a high-voltage transistor that is coupled to one of a plurality of bit lines,
 wherein the high-voltage transistor is disposed on the first peripheral circuit region, and   wherein the sensing latch and the cache latch are disposed on the second peripheral circuit region.   
     
     
         7 . The non-volatile memory device of  claim 2 , wherein the first page buffer circuit includes a page buffer decoder configured to address and drive the first memory cell array, and
 wherein the page buffer decoder is disposed on the second peripheral circuit region.   
     
     
         8 . The non-volatile memory device of  claim 2 , wherein the first peripheral circuit further includes a first row decoder,
 wherein a portion of the first row decoder is disposed on the first peripheral circuit region,   wherein another portion of the first row decoder is disposed on the second peripheral circuit region,   wherein the second peripheral circuit further includes a second row decoder, and   wherein the second row decoder is disposed on the second region.   
     
     
         9 . The non-volatile memory device of  claim 2 , wherein the first semiconductor layer further includes a row decoder coupled to the first plurality of word lines, and
 wherein the second peripheral circuit region overlaps the row decoder in the vertical direction.   
     
     
         10 . The non-volatile memory device of  claim 2 , wherein the first semiconductor layer further includes a pass transistor circuit coupled to the first plurality of word lines,
 wherein the first peripheral circuit further includes a row decoder coupled to the pass transistor circuit, and   wherein the second peripheral circuit region overlaps the pass transistor circuit in the vertical direction.   
     
     
         11 . The non-volatile memory device of  claim 1 , wherein the first peripheral circuit includes a row decoder coupled to the first plurality of word lines,
 wherein a portion of the row decoder is disposed on the first peripheral circuit region, and   wherein another portion of the row decoder is disposed on the second peripheral circuit region.   
     
     
         12 . The non-volatile memory device of  claim 11 , wherein the first semiconductor layer further includes a page buffer circuit coupled to the first plurality of memory cells through a plurality of bit lines, and
 wherein the second peripheral circuit region overlaps the page buffer circuit in the vertical direction.   
     
     
         13 . The non-volatile memory device of  claim 1 , wherein the second semiconductor layer further includes a pad region in which a plurality of bonding pads are disposed, and wherein the pad region does not overlap the first cell region and the second cell region. 
     
     
         14 .- 15 . (canceled) 
     
     
         16 . The non-volatile memory device of  claim 1 , wherein the second semiconductor layer further includes an external peripheral circuit including a data input/output buffer, and
 wherein the external peripheral circuit does not overlap the first cell region and the second cell region.   
     
     
         17 . The non-volatile memory device of  claim 1 , wherein the first peripheral circuit includes a first page buffer circuit and a second page buffer circuit that are coupled to the first memory cell array,
 wherein the first page buffer circuit completely overlaps the first cell region in the vertical direction, and wherein the second page buffer circuit partially overlaps the first cell region in the vertical direction.   
     
     
         18 . The non-volatile memory device of  claim 17 , wherein the second page buffer circuit includes a sensing latch, a cache latch, a high-voltage transistor, and a page buffer decoder,
 wherein the sensing latch and the high-voltage transistor overlap the first cell region in the vertical direction, and   wherein the cache latch and the page buffer decoder do not overlap the first cell region in the vertical direction.   
     
     
         19 . The non-volatile memory device of  claim 1 , wherein the first peripheral circuit includes a first page buffer circuit and a second page buffer circuit that are coupled to the first memory cell array, and
 wherein the first page buffer circuit and the second page buffer circuit partially overlap the first cell region in the vertical direction.   
     
     
         20 . A non-volatile memory device, comprising:
 a first semiconductor layer that includes:
 a memory cell array disposed on a cell region of the first semiconductor layer, wherein the memory cell array includes a plurality of word lines stacked in a vertical direction and a plurality of memory cells respectively coupled to the plurality of word lines; and 
 a first metal pad; and 
   a second semiconductor layer that includes:
 a peripheral circuit disposed on a peripheral circuit region of the second semiconductor layer; and 
 a second metal pad, 
   wherein the second semiconductor layer is coupled, in the vertical direction, to the first semiconductor layer by the first metal pad and the second metal pad in a bonding manner,   wherein the peripheral circuit region includes a first peripheral circuit region that overlaps the cell region in the vertical direction, and a second peripheral circuit region that does not overlap the cell region in the vertical direction,   wherein an area of the peripheral circuit region is greater than an area of the cell region,   wherein the peripheral circuit includes a page buffer circuit connected to the plurality of memory cells through a plurality of bit lines,   wherein a portion of the page buffer circuit is disposed on the first peripheral circuit region, and   wherein another portion of the page buffer circuit is disposed on the second peripheral circuit region.   
     
     
         21 . The non-volatile memory device of  claim 20 , wherein the page buffer circuit includes a sensing latch and a cache latch,
 wherein the sensing latch is disposed on the first peripheral circuit region, and   wherein the cache latch is disposed on the second peripheral circuit region.   
     
     
         22 .- 23 . (canceled) 
     
     
         24 . A non-volatile memory device, comprising:
 a first semiconductor layer that includes a cell region on which a memory cell array is disposed, and a first metal pad, wherein the memory cell array includes a plurality of word lines stacked in a vertical direction and a plurality of memory cells respectively coupled to the plurality of word lines; and   a second semiconductor layer that includes a peripheral circuit region on which a peripheral circuit is disposed, and a second metal pad, wherein the second semiconductor layer is coupled, in the vertical direction, to the first semiconductor layer by the first metal pad and the second metal pad in a bonding manner,   wherein the peripheral circuit region includes a first peripheral circuit region that overlaps the cell region in the vertical direction, and a second peripheral circuit region that does not overlap the cell region in the vertical direction,   wherein an area of the peripheral circuit region is greater than an area of the cell region,   wherein the peripheral circuit further includes a row decoder connected to the plurality of word lines,   wherein a portion of the row decoder is arranged in the first peripheral circuit region, and   wherein another portion of the row decoder is arranged in the second peripheral circuit region.