Baud-rate clock recovery lock point control

Abstract

A baud-rate phase detector uses two error samplers. One error sampler is used to determine whether the sampling time is too early error detection. The other is used to determine whether sampling time is too late. The early error sampler is configured to use a first threshold voltage. The late error sampler is configured to use a second threshold voltage. By adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.

1 . (canceled) 
     
     
         2 . An integrated circuit, comprising:
 a plurality of samplers to produce at least a first early error sample value by comparing, at a first sampling time, a data signal to a first error threshold voltage, to produce at least a first data sample value by comparing, at the first sampling time, the data signal to at least a first data threshold voltage, to produce at least a first late error sample value by comparing, at a second sampling time, the data signal to a second error threshold voltage, and to produce at least a second data sample value by comparing, at the second sampling time, the data signal to at least the first data threshold voltage;   circuitry to generate a first early error sample value based on the first early error sample value and the first data sample value, and to generate a first late error sample value based on the first late error sample value and the second data sample value; and   phase adjustment circuitry to, based on the first early error sample value and the first late error sample value, adjust a phase relationship between the data signal and a timing reference signal that determined the first sampling time and the second sampling time.   
     
     
         3 . The integrated circuit of  claim 2 , wherein the first sampling time and the second sampling time are different in time by an integer multiple of a symbol period of the data signal, the integer multiple being greater than or equal to zero. 
     
     
         4 . The integrated circuit of  claim 2 , wherein the first data sample value is produced by also comparing, at the first sampling time, the data signal to at least a second data threshold voltage, and wherein the second data sample value is produced by also comparing, at the second sampling time, the data signal to at least the second data threshold voltage. 
     
     
         5 . The integrated circuit of  claim 2 , wherein the first early error sample value is further based on a third data sample value and a fourth data sample value, and the first late error sample value is further based on a fifth data sample value and a sixth data sample value. 
     
     
         6 . The integrated circuit of  claim 5 , wherein the plurality of samplers are to:
 produce the third data sample value by comparing, at a third sampling time, the data signal to at least the first data threshold voltage, the third sampling time to be a symbol period of the data signal immediately before the first sampling time;   produce the fourth data sample value by comparing, at a fourth sampling time, the data signal to at least the first data threshold voltage, the fourth sampling time to be a symbol period of the data signal immediately after the first sampling time;   produce the fifth data sample value by comparing, at a fifth sampling time, the data signal to at least the first data threshold voltage, the fifth sampling time to be a symbol period of the data signal immediately before the second sampling time; and   produce the sixth data sample value by comparing, at a sixth sampling time, the data signal to at least the first data threshold voltage, the sixth sampling time to be a symbol period of the data signal immediately after the second sampling time.   
     
     
         7 . The integrated circuit of  claim 2 , wherein, based on the first early error sample value and the first late error sample value, the phase adjustment circuitry is to adjust a phase difference between the data signal and a timing reference signal that determined the first sampling time and the second sampling time to a first phase difference value. 
     
     
         8 . The integrated circuit of  claim 7 , further comprising:
 control circuitry to, while the phase difference between the data signal and the timing reference is operating at the first phase difference value, determine a performance indicator.   
     
     
         9 . The integrated circuit of  claim 8 , wherein the performance indicator is to be based on at least a bit error rate of a received version of the data signal. 
     
     
         10 . The integrated circuit of  claim 8 , wherein the performance indicator is to be based at least on a measurement of a vertical eye opening of a received version of the data signal. 
     
     
         11 . An integrated circuit, comprising:
 a digital to analog converter (DAC) to produce, at a DAC output, a plurality of error sampler threshold voltages;   a data sampler to compare a data signal to a data threshold voltage to produce a plurality of data samples;   an error sampler to compare the data signal to the DAC output to produce a first error sample; and   phase adjustment circuitry to, based on the first error sample and the plurality of data samples, adjust a phase difference between a timing reference and a clock signal that determines a timing that the data sampler and the error sampler sample the data signal.   
     
     
         12 . The integrated circuit of  claim 11 , wherein the first error sample is based on a comparison of the data signal to an early threshold voltage produced by the DAC. 
     
     
         13 . The integrated circuit of  claim 12 , wherein the first error sample is based on a comparison of the data signal to a late threshold voltage produced by the DAC. 
     
     
         14 . The integrated circuit of  claim 13 , further comprising:
 control circuitry to adjust the early threshold voltage and the late threshold voltage to optimize a figure-of-merit.   
     
     
         15 . The integrated circuit of  claim 14 , wherein adjusting the early threshold voltage and the late threshold voltage is to control a phase difference of the clock signal relative to transitions on the data signal. 
     
     
         16 . A method of operating an integrated circuit, comprising:
 comparing, at a first sampling time, a data signal to a first error threshold voltage to produce a first early error sample value;   comparing, at the first sampling time, the data signal to at least a first data threshold voltage to produce a first data sample value;   comparing, at a second sampling time, the data signal to a second error threshold voltage to produce a first late error sample value;   comparing, at the second sampling time, the data signal to at least the first data threshold voltage to produce a second data sample value;   based on the first early error sample value and the first data sample value, producing a first early error sample value;   based on the first late error sample value and the second data sample value, producing a first late error sample value; and   based on the first early error sample value and the first late error sample value, adjusting a phase relationship between the data signal and a timing reference signal that determines the first sampling time and the second sampling time.   
     
     
         17 . The method of  claim 16 , wherein the adjusting of the phase relationship between the data signal and the timing reference signal is to adjust a phase difference between the data signal and the timing reference signal to a first phase difference value. 
     
     
         18 . The method of  claim 17 , further comprising:
 while the phase difference between the data signal and the timing reference signal is operating at the first phase difference value, measuring a performance indicator.   
     
     
         19 . The method of  claim 18 , wherein the performance indicator is to be based on at least a bit error rate of a received version of the data signal. 
     
     
         20 . The method of  claim 18 , wherein the performance indicator is to be based at least on a measurement of a vertical eye opening of a received version of the data signal. 
     
     
         21 . The method of  claim 18 , further comprising:
 controlling a digital-to-analog converter to produce the first error threshold voltage and the second error threshold voltage.