Semiconductor substrate with passivated full deep-trench isolation

Abstract

An image sensor with passivated full deep-trench isolation includes a semiconductor substrate, the substrate including a plurality of sidewalls that form a plurality of trenches that separates pixels of a pixel array, each of the plurality of trenches extending from a first surface of the semiconductor substrate to a second surface opposite the first surface, and a passivation layer disposed on the second surface, the passivation layer lining the plurality of sidewall surfaces and the back surface of the semiconductor substrate. Each of the plurality of trenches extending from the first surface into the semiconductor substrate forming a first opening proximate to the first surface and a second opening proximate to the second surface, wherein the first opening has a width greater than that of the second opening.

What is claimed is: 
     
         1 . An image sensor with passivated full deep-trench isolation, comprising:
 a semiconductor substrate including a pixel array and having a front surface and a back surface that is opposite the front surface and is separated by a substrate thickness;   wherein the semiconductor substrate has a plurality of sidewall surfaces that form, in the semiconductor substrate within the pixel array, a plurality of trenches, each pair of adjacent pixels of the pixel array separated by a trench of the plurality of trenches, each of the plurality of trenches extending substantially perpendicular to and away from the front surface and into the semiconductor substrate a distance equal to the substrate thickness; and   a passivation layer continuously lining the back surface and the plurality of sidewall surfaces.   
     
     
         2 . The image sensor of  claim 1 , each of the plurality of trenches having a front opening that is proximate to the front surface and a back opening that is proximate to the back surface, the front opening having a larger width than the back opening. 
     
     
         3 . The image sensor of  claim 1 , further comprising an anti-reflective coating disposed on the passivation layer and the anti-reflective coating continuously lining the back surface and the plurality of sidewall surfaces. 
     
     
         4 . The image sensor of  claim 1 , each of the plurality of trenches being filled from the back surface with a dielectric material. 
     
     
         5 . The image sensor of  claim 1 , each of the plurality of trenches being filled from the back surface with a conductive material. 
     
     
         6 . The image sensor of  claim 1 , further comprising:
 a circuit layer disposed on the front surface, wherein the passivation layer is in direct contact with the circuit layer disposed; and   a logic wafer bonded to the circuit layer.   
     
     
         7 . An image sensor including a semiconductor substrate having a first surface and a second surface that is opposite the first surface, the image sensor comprising:
 a pixel array having a plurality of pixels disposed on the semiconductor substrate;   a plurality of trenches in the semiconductor substrate arranged within the pixel array separating adjacent pixels, each of the plurality of trenches extending from the first surface into the semiconductor substrate forming a first opening proximate to the first surface and a second opening proximate to the second surface, wherein the first opening has a width greater than that of the second opening; and   a first material layer disposed on the second surface, the first material layer being continuously lining the second surface and a plurality of sidewall surfaces of the plurality of trenches.   
     
     
         8 . The image sensor of  7 , wherein the first material layer is a high υ dielectric material layer. 
     
     
         9 . The image sensor of  7 , wherein the plurality of sidewall surfaces are formed from the first surface of the semiconductor substrate and a distance that each of the plurality of trenches extends into the semiconductor substrate is equal to a substrate thickness of the semiconductor substrate. 
     
     
         10 . The image sensor of  7 , wherein the plurality of trenches is interconnected forming a trench grid separating the plurality of pixels, wherein each of the trenches having a width decreasing with an increasing distance from the first surface toward the second surface. 
     
     
         11 . The image sensor of  7 , further comprising a second material layer disposed on the first material layer, the second material layer continuously lining the second surface and the plurality of sidewall surfaces of the plurality of trenches. 
     
     
         12 . The image sensor of  11 , the second material layer having a different material composition than that of the first material layer. 
     
     
         13 . The image sensor of  7 , wherein the first material layer is in contact with a dielectric layer disposed on the first surface. 
     
     
         14 . The image sensor of  13 , further comprising a circuit layer that includes a multi-layer interconnection structure embedded in the dielectric layer. 
     
     
         15 . An image sensor, comprising:
 a semiconductor substrate having a first surface and a second surface that is opposite the first surface;   a plurality of photodiode regions disposed on the semiconductor substrate;   a trench in the semiconductor substrate arranged separating at least a pair of adjacent photodiode regions, the trench extending from the first surface into the semiconductor substrate forming a first opening proximate to the first surface and a second opening proximate to the second surface; and   a first material layer having negative fixed charges disposed on the second surface, the first material layer being continuously lining the second surface and a plurality of surfaces of the trench, wherein the first material layer is disposed onto a first inter-layer dielectric layer of a circuit layer disposed on the first surface.   
     
     
         16 . The image sensor of  15 , further comprising a second material layer disposed on the first material layer, the second material layer continuously lining the second surface and the plurality of surfaces of the trench. 
     
     
         17 . The image sensor of  16 , wherein the trench has a fill material disposed on the second material layer. 
     
     
         18 . The image sensor of  15 , wherein the first opening has a width greater than that of the second opening. 
     
     
         19 . The image sensor of  18 , wherein the trench has an aspect ratio between 12.5:1 and 20:1. 
     
     
         20 . The image sensor of  15 , further comprising a plurality of transistor gates embedded in the first inter-layer dielectric layer.