Point to point connected processing elements with data joiner components

Abstract

A system comprises a first processing element, a second processing element, a point-to-point connection between the first processing element and the second processing element, and a communication bus connecting together at least the first processing element and the second processing element. The first processing element includes a first matrix computing unit and the second processing element includes a second matrix computing unit. The point-to-point connection is configured to provide at least a result of the first processing element to a data joiner component of the second processing element configured to join at least the provided result of the first processing element with a result of the second matrix computing unit.

What is claimed is: 
     
         1 . A system, comprising:
 a first processing element including a first matrix computing unit;   a second processing element including a second matrix computing unit;   a point-to-point connection between the first processing element and the second processing element, wherein the point-to-point connection is configured to provide at least a first processing result of the first processing element to a data joiner component of the second processing element configured to join at least the first processing result of the first processing element with a second processing result of the second matrix computing unit to create a packed result, wherein the first processing result of the first matrix computing unit and the second processing result of the second matrix computing unit are byte-aligned in the packed result; and   a communication bus connecting together at least the first processing element and the second processing element.   
     
     
         2 . The system of  claim 1 , wherein the data joiner component includes an adder and a multiplexer. 
     
     
         3 . The system of  claim 2 , wherein the multiplexer is configured to shift the second processing result of the second matrix computing unit by a configured result offset. 
     
     
         4 . The system of  claim 3 , wherein the configured result offset is a 0-byte, 8-byte, 16-byte, or 24-byte offset. 
     
     
         5 . The system of  claim 3 , wherein the configured result offset is specified by a processing element instruction. 
     
     
         6 . The system of  claim 5 , wherein the processing element instruction includes a convolution operation instruction. 
     
     
         7 . The system of  claim 5 , wherein the second processing element is configured to receive the processing element instruction via the communication bus. 
     
     
         8 . The system of  claim 3 , wherein the adder is configured to receive the first processing result of the first processing element and the shifted result of the second matrix computing unit. 
     
     
         9 . The system of  claim 8 , wherein the adder is configured to add together the first processing result of the first processing element and the shifted result of the second matrix computing unit to output the packed result. 
     
     
         10 . The system of  claim 9 , wherein the packed result is a size of a cache-line. 
     
     
         11 . The system of  claim 9 , further comprising a second point-to-point connection configured to send the packed result to a third processing element, and wherein the second point-to-point connection connects the second matrix computing unit to the third processing element. 
     
     
         12 . The system of  claim 11 , wherein the third processing element includes a second data joiner component and the second data joiner component is connected to the second point-to-point connection. 
     
     
         13 . The system of  claim 9 , wherein the packed result includes a plurality of matrix compute results, and each matrix compute result of the plurality of matrix compute results is determined using a different processing element. 
     
     
         14 . The system of  claim 1 , wherein the system is included in an integrated circuit chip. 
     
     
         15 . A method, comprising:
 determining a processing result using a first processing element, wherein the first processing element includes a first matrix computing unit;   providing the processing result of the first processing element to a data joiner component of a second matrix computing unit via a first point-to-point connection;   determining a result of the second matrix computing unit;   providing the result of the second matrix computing unit to the data joiner component of the second matrix computing unit; and   joining at least the first processing result of the first processing element with a second processing result of the second matrix computing unit to create a packed result, wherein the first processing result of the first matrix computing unit and the second processing result of the second matrix computing unit are byte-aligned in the packed result.   
     
     
         16 . The method of  claim 15 , wherein the data joiner component includes an adder and a multiplexer. 
     
     
         17 . The method of  claim 16 , wherein the multiplexer is configured to shift the result of the second matrix computing unit by a configured result offset. 
     
     
         18 . The method of  claim 16 , wherein the packed result includes a plurality of matrix compute results, and each matrix compute result of the plurality of matrix compute results is determined using a different processing element. 
     
     
         19 . A system, comprising:
 a first processing element including a first matrix computing unit and a first data joiner component;   a second processing element including a second matrix computing unit and a second data joiner component;   a third processing element including a third matrix computing unit and a third data joiner component;   a first point-to-point connection between the first data joiner component of the first processing element and the second data joiner component of the second processing element, wherein the first point-to-point connection is configured to provide at least a first output result of the first data joiner component to the second data joiner component, and wherein the second data joiner component is configured to output a second output result by combining at least the first output result with a compute result of the second matrix computing unit; and   a second point-to-point connection between the second data joiner component of the second processing element and the third data joiner component of the third processing element, wherein the second point-to-point connection is configured to provide at least the second output result of the second data joiner component to the third data joiner component.   
     
     
         20 . The system of  claim 19 , wherein the first data joiner component includes an adder and a multiplexer.