Sensing circuit and sensing method

Abstract

The sensing circuit comprises a plurality of first transceiver capacitors and a plurality of second transceiver capacitors. The plurality of first transceiver capacitors are configured to send and receive a plurality of first detection signals. The plurality of second transceiver capacitors, configured to send and receive a plurality of second detection signals. During a self-capacitance mode, the plurality of first transceiver capacitors are configured to output the plurality of first detection signals and receive the plurality of first detection signals, and the plurality of second transceiver capacitors are configured to output the plurality of second detection signals and receive the plurality of second detection signals. During a mutual-capacitance mode, the plurality of first transceiver capacitors are configured to output the plurality of first detection signals, and the plurality of second transceiver capacitors are configured to receive the plurality of first detection signals.

What is claimed is: 
     
         1 . A sensing circuit, comprising:
 a plurality of first transceiver capacitors, configured to send and receive a plurality of first detection signals, and the plurality of first detection signals are independent of each other; and   a plurality of second transceiver capacitors, configured to send and receive a plurality of second detection signals, and the plurality of second detection signals are independent of each other, wherein the plurality of first transceiver capacitors and the plurality of second transceiver capacitors are alternately arranged to form an array,   wherein during a self-capacitance mode, the plurality of first transceiver capacitors are configured to output the plurality of first detection signals and receive the plurality of first detection signals, and the plurality of second transceiver capacitors are configured to output the plurality of second detection signals and receive the plurality of second detection signals,   wherein during a mutual-capacitance mode, the plurality of first transceiver capacitors are configured to output the plurality of first detection signals, and the plurality of second transceiver capacitors are configured to receive the plurality of first detection signals,   wherein the plurality of first transceiver capacitors are not adjacent to each other on any row and any column of the array, and the plurality of first transceiver capacitors are adjacent to each other on any diagonal, any subdiagonal, and any superdiagonal of the array, wherein the plurality of second transceiver capacitors are not adjacent to each other on the any row and the any column of the array, and the plurality of second transceiver capacitors are adjacent to each other on the any diagonal, the any subdiagonal, and the any superdiagonal of the array.   
     
     
         2 . The sensing circuit of  claim 1 , wherein each of the plurality of first transceiver capacitors comprises a first capacitor, wherein each of the plurality of second transceiver capacitors comprises a second capacitor. 
     
     
         3 . The sensing circuit of the  claim 2 , wherein the first capacitor is coupled to the second capacitor in a first row of the array. 
     
     
         4 . The sensing circuit of  claim 3 , wherein during the self-capacitance mode, the first capacitor is configured to output a first self-capacitance sensing signal and receive the first self-capacitance sensing signal, and the second capacitor is configured to output a second self-capacitance sensing signal and receive the second self-capacitance sensing signal. 
     
     
         5 . The sensing circuit of  claim 4 , wherein during the mutual-capacitance mode, the first capacitor is configured to output a first mutual-capacitance sensing signal, and the second capacitor is configured to receive the first mutual-capacitance sensing signal. 
     
     
         6 . The sensing circuit of  claim 4 , wherein each of the plurality of first transceiver capacitors further comprises a third capacitor, wherein each of the plurality of second transceiver capacitors further comprises a fourth capacitor. 
     
     
         7 . The sensing circuit of  claim 6 , wherein the third capacitor is coupled to the second capacitor in the first row of the array, wherein the fourth capacitor is coupled to the third capacitor in the first row of the array. 
     
     
         8 . The sensing circuit of  claim 7 , wherein during the self-capacitance mode, the third capacitor is configured to output a third self-capacitance sensing signal and receive the third self-capacitance sensing signal, and the fourth capacitor is configured to output a fourth self-capacitance sensing signal and receive the fourth self-capacitance sensing signal. 
     
     
         9 . The sensing circuit of  claim 8 , wherein during the mutual-capacitance mode, the third capacitor is configured to output a second mutual-capacitance sensing signal, and the fourth capacitor is configured to receive the second mutual-capacitance sensing signal. 
     
     
         10 . The sensing circuit of  claim 9 , wherein during a first self-capacitance operation period of the self-capacitance mode, the first capacitor is configured to output the first self-capacitance sensing signal and simultaneously receive the first self-capacitance sensing signal, the second capacitor is configured to output the second self-capacitance sensing signal and simultaneously receive the second self-capacitance sensing signal, the third capacitor is configured to output the third self-capacitance sensing signal and simultaneously receive the third self-capacitance sensing signal, and the fourth capacitor is configured to output the fourth self-capacitance sensing signal and simultaneously receive the fourth self-capacitance sensing signal. 
     
     
         11 . The sensing circuit of  claim 10 , wherein during a first mutual-capacitance operation period of the mutual-capacitance mode, the first capacitor is configured to output a first mutual-capacitance sensing signal, the second capacitor is configured to simultaneously receive the first mutual-capacitance sensing signal, the third capacitor is configured to simultaneously output the second mutual-capacitance sensing signal, and the fourth capacitor is configured to simultaneously receive the second mutual-capacitance sensing signal. 
     
     
         12 . The sensing circuit of  claim 2 , wherein the first capacitor is coupled to the second capacitor in a first row of the array, wherein each of the plurality of first transceiver capacitors further comprises a third capacitor, wherein each of the plurality of second transceiver capacitors further comprises a fourth capacitor. 
     
     
         13 . The sensing circuit of  claim 12 , wherein the fourth capacitor is coupled to the first capacitor in a first column of the array. 
     
     
         14 . The sensing circuit of  claim 13 , wherein the third capacitor is coupled to the fourth capacitor in a second row of the array, and the third capacitor is coupled to the second capacitor. 
     
     
         15 . The sensing circuit of  claim 14 , wherein during the self-capacitance mode, the third capacitor is configured to output a third self-capacitance sensing signal and receive the third self-capacitance sensing signal, and the fourth capacitor is configured to output a fourth self-capacitance sensing signal and receive the fourth self-capacitance sensing signal. 
     
     
         16 . The sensing circuit of  claim 15 , wherein during the mutual-capacitance mode, the third capacitor is configured to output a second mutual-capacitance sensing signal, and the fourth capacitor is configured to receive the second mutual-capacitance sensing signal. 
     
     
         17 . The sensing circuit of  claim 16 , wherein during a first self-capacitance operation period of the self-capacitance mode, the first capacitor is configured to output a first self-capacitance sensing signal and simultaneously receive the first self-capacitance sensing signal, the second capacitor is configured to output a second self-capacitance sensing signal and simultaneously receive the second self-capacitance sensing signal, the third capacitor is configured to output the third self-capacitance sensing signal and simultaneously receive the third self-capacitance sensing signal, and the fourth capacitor is configured to output the fourth self-capacitance sensing signal and simultaneously receive the fourth self-capacitance sensing signal. 
     
     
         18 . The sensing circuit of  claim 17 , wherein during a first mutual-capacitance operation period of the mutual-capacitance mode, the first capacitor is configured to output a first mutual-capacitance sensing signal, the second capacitor is configured to simultaneously receive the first mutual-capacitance sensing signal, the third capacitor is configured to simultaneously output the second mutual-capacitance sensing signal, and the fourth capacitor is configured to simultaneously receive the second mutual-capacitance sensing signal. 
     
     
         19 . The sensing circuit of  claim 1 , wherein the self-capacitance mode comprises n self-capacitance operation periods, wherein the mutual-capacitance mode comprises n mutual-capacitance operation periods, wherein n is an integer greater than zero. 
     
     
         20 . A sensing method, comprising:
 sending and receiving a plurality of first detection signals by a plurality of first transceiver capacitors, and the plurality of first detection signals being independent of each other;   sending and receiving a plurality of second detection signals by a plurality of second transceiver capacitors, and the plurality of second detection signals being independent of each other;   during a self-capacitance mode, outputting the plurality of first detection signals and receiving the plurality of first detection signals by the plurality of first transceiver capacitors, and outputting the plurality of second detection signals and receiving the plurality of second detection signals by the plurality of second transceiver capacitors; and   during a mutual-capacitance mode, outputting the plurality of first detection signals by the plurality of first transceiver capacitors, and receiving the plurality of first detection signals by the plurality of second transceiver capacitors.