US2023247214A1PendingUtilityA1

Configurable maximum transform size

Assignee: Tencent America LLCPriority: Mar 22, 2019Filed: Apr 6, 2023Published: Aug 3, 2023
Est. expiryMar 22, 2039(~12.6 yrs left)· nominal 20-yr term from priority
H04N 19/96H04N 19/70H04N 19/439H04N 19/436H04N 19/192H04N 19/176H04N 19/136H04N 19/129H04N 19/119H04N 19/60H04N 19/122H04N 19/44H04N 19/132
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Claims

Abstract

Aspects of the disclosure provide methods and an apparatus including processing circuitry that decodes coded information of a coding block (CB) in a picture from a coded video bitstream. The coded information indicates a width W and a height H of the CB. The processing circuitry partitions the CB into sub-processing units (SPUs) having a width being a minimum one of W and K and a height being a minimum one of H and K. At least one of the width W and the height H is larger than a processing data unit size K. The processing circuitry determines a partitioning structure to partition the SPUs based on the width, the height, and a maximum transform unit (TU) size M. At least one of the width and the height is larger than M. The processing circuitry partitions each of the SPUs into TUs of M×M based on the partitioning structure.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method for video decoding in a decoder, comprising:
 decoding coded information of a coding block (CB) in a picture from a coded video bitstream, the coded information indicating a width of the CB and a height of the CB;   determining a maximum sub-block transform (SBT) size based on an SBT maximum size flag and a configurable maximum transform block size, the SBT maximum size flag indicating a first value responsive to the maximum SBT size being 64, the SBT maximum size flag indicating a second value responsive to the maximum SBT size being 32, and the maximum transform block size being less than 64; and   reconstructing the coding block based on the maximum SBT size.   
     
     
         2 . The method according to  claim 1 , further comprising:
 partitioning the CB into sub-processing units (SPUs) having a width that is a minimum one of the width of the CB and a processing data unit size and a height that is a minimum one of the height of the CB, at least one of the width and the height of the CB being larger than the processing data unit size;   determining a partitioning structure to further partition the SPUs based on the width and the height of the SPUs and the maximum transform block size, at least one of the width and the height of the SPUs being larger than the maximum transform block size; and   partitioning each of the SPUs into TUs of the maximum transform block size based on the determined partitioning structure.   
     
     
         3 . The method of  claim 2 , wherein
 the width and the height of the SPUs are larger than the maximum transform block size;   the determining the partitioning structure includes determining the partitioning structure to be a quadtree partitioning structure; and   the partitioning the SPUs into the TUs includes partitioning the SPUs into the TUs based on the quadtree partitioning structure.   
     
     
         4 . The method of  claim 2 , wherein
 the width of the SPUs is larger than the maximum transform block size and the height of the SPUs is equal to the maximum transform block size;   the determining the partitioning structure includes determining the partitioning structure to be a vertical binary tree partitioning structure; and   the partitioning the SPUs into the TUs includes partitioning the SPUs into the TUs based on the vertical binary tree partitioning structure.   
     
     
         5 . The method of  claim 2 , wherein
 the height of the SPUs is larger than the maximum transform block size and the width of the SPUs is equal to the maximum transform block size;   the determining the partitioning structure includes determining the partitioning structure to be a horizontal binary tree partitioning structure; and   the partitioning the SPUs into the TUs includes partitioning the SPUs into the TUs based on the horizontal binary tree partitioning structure.   
     
     
         6 . The method of  claim 2 , wherein the partitioning the SPUs into the TUs includes partitioning one of the SPUs recursively into the TUs based on the partitioning structure. 
     
     
         7 . The method of  claim 2 , further comprising:
 processing the SPUs according to a first scan order; and   processing the TUs in each of the SPUs according to a second scan order.   
     
     
         8 . The method of  claim 7 , wherein at least one of the first scan order and the second scan order is one of (i) a raster scan order, (ii) a vertical scan order, (iii) a zig-zag order, and (iv) a diagonal scan order. 
     
     
         9 . The method of  claim 8 , wherein the first scan order and the second scan order are the raster scan order. 
     
     
         10 . The method of  claim 7 , wherein
 the width of the CB is 128, the height of the CB is 64, the processing data unit size is 64, and the maximum transform block size is 32;   the first scan order is from left to right; and   the second scan order is a raster scan order.   
     
     
         11 . An apparatus for video decoding, comprising processing circuitry configured to:
 decode coded information of a coding block (CB) in a picture from a coded video bitstream, the coded information indicating a width of the CB and a height of the CB;   determine a maximum sub-block transform (SBT) size based on an SBT maximum size flag and a configurable maximum transform block size, the SBT maximum size flag indicating a first value responsive to the maximum SBT size being 64, the SBT maximum size flag indicating a second value responsive to the maximum SBT size being 32, and the maximum transform block size being less than 64; and   reconstruct the coding block based on the maximum SBT size.   
     
     
         12 . The apparatus according to  claim 11 , wherein the processing circuitry is configured to:
 partition the CB into sub-processing units (SPUs) having a width that is a minimum one of the width of the CB and a processing data unit size and a height that is a minimum one of the height of the CB, at least one of the width and the height of the CB being larger than the processing data unit size;   determine a partitioning structure to further partition the SPUs based on the width and the height of the SPUs and the maximum transform block size, at least one of the width and the height of the SPUs being larger than the maximum transform block size; and   partition each of the SPUs into TUs of the maximum transform block size based on the determined partitioning structure.   
     
     
         13 . The apparatus of  claim 12 , wherein
 the width and the height of the SPUs are larger than the maximum transform block size; and   the processing circuitry is configured to:
 determine the partitioning structure to be a quadtree partitioning structure, and 
   partition the SPUs into the TUs based on the quadtree partitioning structure.   
     
     
         14 . The apparatus of  claim 12 , wherein
 the width of the SPUs is larger than the maximum transform block size and the height of the SPUs is equal to the maximum transform block size; and   the processing circuitry is configured to:
 determine the partitioning structure to be a vertical binary tree partitioning structure, and 
 partition the SPUs into the TUs based on the vertical binary tree partitioning structure. 
   
     
     
         15 . The apparatus of  claim 12 , wherein
 the height of the SPUs is larger than the maximum transform block size and the width of the SPUs is equal to the maximum transform block size; and   the processing circuitry is configured to:
 determine the partitioning structure to be a horizontal binary tree partitioning structure, and 
 partition the SPUs into the TUs based on the horizontal binary tree partitioning structure. 
   
     
     
         16 . The apparatus of  claim 12 , wherein the processing circuitry is configured to partition one of the SPUs recursively into the TUs based on the partitioning structure. 
     
     
         17 . The apparatus of  claim 12 , wherein the processing circuitry is configured to:
 process the SPUs according to a first scan order; and   process the TUs in each of the SPUs according to a second scan order.   
     
     
         18 . The apparatus of  claim 17 , wherein at least one of the first scan order and the second scan order is one of (i) a raster scan order, (ii) a vertical scan order, (iii) a zig-zag order, and (iv) a diagonal scan order. 
     
     
         19 . The apparatus of  claim 18 , wherein the first scan order and the second scan order are the raster scan order. 
     
     
         20 . The apparatus of  claim 17 , wherein
 the width of the CB is 128, the height of the CB is 64, the processing data unit size is 64, and the maximum transform block size is 32;   the first scan order is from left to right; and   the second scan order is a raster scan order.

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