Vertical trench gate mosfet with integrated schottky diode

Abstract

An integrated circuit includes a trench gate MOSFET including MOSFET cells. Each MOSFET cell includes an active trench gate in an n-epitaxial layer oriented in a first direction with a polysilicon gate over a lower polysilicon portion. P-type body regions are between trench gates and are separated by an n-epitaxial region. N-type source regions are located over the p-type regions. A gate dielectric layer is between the polysilicon gates and the body regions. A metal-containing layer contacts the n-epitaxial region to provide an anode of an embedded Schottky diode. A dielectric layer over the n-epitaxial layer has metal contacts therethrough connecting to the n-type source regions, to the p-type body regions, and to the anode of the Schottky diode.

1 . A method of fabricating an integrated circuit, comprising;
 forming a first vertical trench gate transistor within an n-type semiconductor substrate having a top surface, the first trench gate transistor comprising:
 a first n-type region located at the top surface and between a first trench gate and a metal contact; and 
 a first p-type region located between the first n-type region and the n-type substrate; 
   forming a second vertical trench gate transistor within the n-type semiconductor substrate, the second trench gate transistor comprising:
 a second n-type region located at the top surface and between the first trench gate and the metal contact; and 
 a second p-type region located between the second n-type region and the n-type substrate, and 
   forming a Schottky contact to the n-type substrate, thereby forming a Schottky diode between the first and second trench gate transistors, the Schottky contact comprising a metal-containing layer located directly on the n-type substrate, and   electrically connecting to the first trench gate transistor, to the second trench gate transistor, and to the Schottky diode.   
     
     
         2 . The method of  claim 1 , wherein the metal-containing layer comprises TiN or TaN. 
     
     
         3 . The method of  claim 1 , wherein the first and second n-type regions are configured to operate as first and second source regions, respectively, of the first and second vertical trench gate transistors. 
     
     
         4 . The method of  claim 1 , wherein the first and second vertical trench gate transistors include respective first and second polysilicon gates, and further comprising forming a recess in each of the first and second polysilicon gates. 
     
     
         5 . The method of  claim 1 , wherein the metal-containing layer connects the first n-type region to the first p-type region, and connects the second n-type region to the second p-type region. 
     
     
         6 . The method of  claim 1 , wherein the forming the Schottky contact includes etching through the first and second n-type regions and into the first and second p-type regions. 
     
     
         7 . The method of  claim 1 , wherein a thickness of the metal-containing layer is within a range between about 10 nm and about 50 nm. 
     
     
         8 . The method of  claim 1 , wherein the Schottky contact is located on the top surface of the semiconductor substrate. 
     
     
         9 . An integrated circuit, comprising:
 an n-type substrate having an n-type epitaxial layer thereon;   a plurality of active trench gate MOSFET cells in an active area each including a corresponding one of a plurality of active trench gates in the epitaxial layer, each active trench gate having a trench dielectric layer filled with a polysilicon gate over a spaced apart lower polysilicon portion;   p-type body regions in an upper portion of the epitaxial layer between adjacent ones of the plurality of the active trench gates, adjacent pairs of p-type body regions having one of a plurality of surface regions of the epitaxial layer located therebetween;   n-type source regions at a top surface of the substrate within the body regions;   a metal-containing layer located directly on the surface regions of the epitaxial layer, and   a metal layer over the metal-containing layer that electrically connects the p-type body regions, the n-type source regions and the surface regions.   
     
     
         10 . The integrated circuit of  claim 9 , wherein each of the active trench gates has a double shield field plate. 
     
     
         11 . The integrated circuit of  claim 9 , wherein the metal-containing layer comprises TiN or TaN. 
     
     
         12 . The integrated circuit of  claim 9 , wherein the substrate provide a drain for the trench gate MOSFET cells. 
     
     
         13 . The integrated circuit of  claim 9 , further comprising an outer junction termination trench that provides a junction termination region which surrounds the active area. 
     
     
         14 . The integrated circuit of  claim 9 , wherein each of the polysilicon gates includes a top recess. 
     
     
         15 . The integrated circuit of  claim 9 , wherein the metal-containing layer extends through each of the n-type source regions and into a corresponding one of the p-type body regions. 
     
     
         16 . The integrated circuit of  claim 9 , wherein a thickness of the metal-containing layer is within a range of about 10 nm to about 50 nm. 
     
     
         17 . The integrated circuit of  claim 9 , wherein the top surfaces of the surface regions of the epitaxial layer are coplanar with the top surface of the epitaxial layer. 
     
     
         18 . An integrated circuit, comprising:
 first and second trench plates formed in a lightly-doped n-type semiconductor substrate having a surface;   a first p-type region intersecting the substrate surface and extending from the first trench plate to the second trench plate;   a second p-type region intersecting the substrate surface and extending from the first trench plate to the second trench plate;   an n-type substrate portion intersecting the substrate surface between the first and second p-type regions and extending from the first trench plate to the second trench plate; and   a metal-containing layer located between the first and second trench plate and directly on the n-type substrate portion.   
     
     
         19 . The integrated circuit of  claim 18 , wherein the first p-type region includes first and second surface regions that intersect the substrate surface, and further comprising an n-type region located within the first p-type region and between the first and second surface regions. 
     
     
         20 . The integrated circuit of  claim 18 , further comprising a third p-type region located between the first and second trenches, and a second substrate portion intersecting the substrate between the second and third p-type regions, wherein the metal-containing layer connects to the first and second p-type regions and to the n-type substrate portion.