Fin field effect transistor with merged drift region

Abstract

A fin field effect transistor (FinFET) includes a drain region, a merged drift region, and a plurality of fins. The drain region extends above a surface of a semiconductor substrate and has a first dopant concentration of first conductivity type. The merged drift region extends above the substrate surface and touches the drain region, and has a second lower dopant concentration of the first conductivity type. The plurality of fins extend above the substrate surface and each fin is directly connected to the merged drift region. Each fin is connected to a source region having the first conductivity type at a distal end of that fin from the merged drift region.

What is claimed is: 
     
         1 . A fin field effect transistor (FinFET), comprising:
 a drain region having a first dopant concentration of a first conductivity type that extends above a surface of a semiconductor substrate;   a merged drift region having a second lower dopant concentration of the first conductivity type that extends above the substrate surface and touches the drain region;   a plurality of fins extending above the substrate surface and each directly connected to the merged drift region, each fin connected to a source region having the first conductivity type at a distal end of that fin from the merged drift region.   
     
     
         2 . The FinFET of  claim 1 , further comprising a field plate oxide layer formed over the merged drift region. 
     
     
         3 . The FinFET of  claim 2  wherein each fin includes:
 a fin drift region having the first conductivity type and extending from the merged drift region; 
 a body region having a second opposite conductivity type and forming a junction with the fin drift region; and 
 a gate oxide layer formed over the body region. 
 
     
     
         4 . The FinFET of  claim 2 , wherein the field plate oxide layer has a sidewall with a concave surface. 
     
     
         5 . The FinFET of  claim 3 , further comprising a gate electrode formed over the gate oxide layer, wherein a portion of the merged drift region is not covered by the gate electrode. 
     
     
         6 . The FinFET of  claim 1 , wherein the source region is connected to the plurality of fins. 
     
     
         7 . The FinFET of  claim 1 , wherein the source region is connected to a back gate region that has a second opposite conductivity type, the back gate region touching the source region. 
     
     
         8 . A method for fabricating a fin field effect transistor (FinFET), comprising:
 removing portions of a semiconductor substrate to produce a drain region, a plurality of fins, and a merged drift region touching the drain region and each of the fins at a proximal end, each fin having a distal end opposite the proximal end;   doping the merged drift region with a dopant of a first conductivity type;   doping a source region at the distal end with a dopant of the first conductivity type; and   doping a body region of each fin between the source region and the merged drift region with a dopant of a second opposite conductivity type.   
     
     
         9 . The method of  claim 8 , further comprising:
 forming a dielectric layer on the drain region, the merged drift region, and the plurality of fins; and   etching the dielectric layer to form a field plate oxide layer over the merged drift region.   
     
     
         10 . The method of  claim 8 , wherein the drain region and the merged drift region have a same dopant concentration. 
     
     
         11 . The method of  claim 9 , wherein:
 the dielectric layer is a first dielectric layer; and   the method further comprises:
 forming a second dielectric layer on each of the fins; 
 etching the second dielectric layer to form a gate oxide layer over the body region of each of the fin. 
   
     
     
         12 . The method of  claim 9 , wherein etching the dielectric layer includes forming a concave sidewall surface of the field plate oxide layer. 
     
     
         13 . The method of  claim 11 , further comprising forming a gate electrode on the gate oxide layer of each of the plurality of fins. 
     
     
         14 . The method of  claim 8 , further comprising forming, for each fin, a back gate region that has the second opposite conductivity type, the back gate region touching the source region. 
     
     
         15 . The method of  claim 8 , further comprising:
 filling a space about the plurality of fins with a dielectric material; and   etching the dielectric material to expose a portion of each fin.   
     
     
         16 . An integrated circuit comprising:
 a semiconductor substrate;   a fin field effect transistor (FinFET) formed in or over the semiconductor substrate,
 the FinFET including:
 a merged drift region having a first conductivity type extending above the substrate; 
 first and second fins extending upward from the substrate and from the merged drift region laterally over the substrate; and 
 a drain region extending upward from the substrate and from the merged drift region laterally over the substrate. 
 
   
     
     
         17 . The integrated circuit of  claim 16 , wherein:
 the first fin comprises:
 a first fin drift region having the first conductivity type; 
 a first body region having a second opposite conductivity type adjacent the first fin drift region; and 
 a first gate oxide layer over the first fin drift region; and 
   the second fin comprises:
 a second fin drift region having the first conductivity type; 
 a second body region having the second opposite conductivity type adjacent the second fin drift region; and 
 a second gate oxide layer over the second fin drift region. 
   
     
     
         18 . The integrated circuit of  claim 17 , wherein the field plate oxide layer has a sidewall with a concave surface. 
     
     
         19 . The integrated circuit of  claim 16 , further comprising a source region connected to the first and second fins. 
     
     
         20 . The integrated circuit of  claim 16 , further comprising a first source region located in the first fin and a second source region located in the second fin. 
     
     
         21 . The integrated circuit of  claim 16 , further comprising a gate electrode located over a portion of the merged drift region less than a whole of the merged drift region.