Gate structure for semiconductor devices

Abstract

A semiconductor structure is disclosed, including a first gate and a second gate aligned with the first gate, a first gate via, a second gate via, multiple conductive segments, and a first conductive line. The first gate via is disposed on the first gate and the second gate via is disposed on the second gate. The first and second gates are configured to be a terminal of a first logic circuit, which is coupled to a terminal of a second logic circuit. The first conductive line is coupled to the first gate through a first connection via and the first gate via and is electrically coupled to the second gate through a second connection via and the second gate via.

What is claimed is: 
     
         1 . A structure, comprising:
 a first gate and a second gate;   at least one first gate via disposed on the first gate and at least one second gate via disposed on the second gate, wherein the at least one first gate via and the at least one second gate via comprise a plurality of first gate vias and a plurality of second gate vias, respectively, and wherein a number of the plurality of first gate vias and a number of the plurality of second gate vias are the same;   a first conductive segment and a second conductive segment connected to the at least one first gate via; and   a conductive line disposed above the first conductive segment.   
     
     
         2 . The structure of  claim 1 , wherein the first and second gates are connected to each other. 
     
     
         3 . The structure of  claim 2 , further comprising a first active area and a second active area separated from each other, wherein the at least one first gate via comprises a plurality of first gate vias aligned along a width of the first active area and the at least one second gate via comprises a plurality of second gate vias aligned along a width of the second active area. 
     
     
         4 . The structure of  claim 2 , further comprising a first active area and a second active area separated from each other, wherein the at least one first gate via aligns with a center of the first active area in the first direction and the second gate via aligns with a center of the second active area. 
     
     
         5 . The structure of  claim 1 , wherein the at least one first gate and the at least one second gate are configured to be a terminal of a logic circuit. 
     
     
         6 . The structure of  claim 1 , further comprising:
 a third gate and a fourth gate aligned with each other;   a third gate via disposed on the third gate and a fourth gate via disposed on the fourth gate; and   a third conductive segment coupled to the third gate and a fourth conductive segment coupled to the fourth gate, wherein the third and fourth gates are configured to be a terminal of an other logic circuit coupled to the logic circuit.   
     
     
         7 . The structure of  claim 1 , wherein the conductive line is disposed above the first conductive segment. 
     
     
         8 . A structure, comprising:
 a first active area and a second active area;   a gate disposed over the first active area and second active area;   first gate vias and second gate vias coupled to the gate, wherein the first gate vias are arranged closer to the first active area than the second gate vias; and   a conductive segment connected to the first gate vias, wherein the first gate vias and the second gate vias comprise a different number of first gate vias and second gate vias, respectively.   
     
     
         9 . The structure of  claim 8 , wherein the first gate vias align with a center of the first active area. 
     
     
         10 . The structure of  claim 8 , further comprising a conductive line disposed above the conductive segment and electrically coupled to the first gate vias and the second gate vias. 
     
     
         11 . The structure of  claim 10 , wherein the gate comprises a first portion and a second portion separated from each other, wherein the first gate vias are disposed on the first portion and the second gate vias are disposed on the second portion. 
     
     
         12 . The structure of  claim 11 , wherein a ratio of width of the conductive line to a width of the first portion of the gate is about 1 to about 20. 
     
     
         14 . The structure of  claim 8 , wherein the first gate vias, the second gate vias, and the conductive line are included in a conductive path. 
     
     
         13 . The structure of  claim 8 , wherein a resistance of the conductive path increases in response to number of first gate vias decreasing. 
     
     
         15 . The structure of  claim 8 , further comprises a source/drain via electrically connected to the conductive segment. 
     
     
         16 . The structure of  claim 8 , further comprising an other gate disposed over the first active area. 
     
     
         17 . A method, comprising:
 forming a gate structure shared by a first transistor and a second transistor;   forming at least one first gate via and at least one second gate via on the gate structure;   forming a first conductive segment and a second conductive segment, wherein:
 the first conductive segment is connected to the at least one gate via and at least one first source/drain via, 
 the second conductive segment is connected to the at least one second gate via and at least one second source/drain via, and 
 the first and second conductive segments are above the gate structure; and 
   forming a conductive line above the first and second conductive segments and coupled to the gate structure through a plurality of conductive vias, a plurality of conductive segments, the at least one first gate via, and the at least one second gate via,
 wherein a ratio of a width of the conductive line to a width of the gate structure ranges from about 1 to about 20. 
   
     
     
         18 . The method of  claim 17 , wherein a ratio of a height of the conductive line to a height of the gate structure ranges from about 1 to about 40. 
     
     
         19 . The method of  claim 17 , further comprising:
 forming a first active area of the first transistor and a second active area of the second transistor that are separated from each other, wherein the at least one first gate via aligns with a center of the first active area.   
     
     
         20 . The method of  claim 17 , wherein a number of the at least one first gate via and a number of the at least one second gate via vary as a length of the gate structure varies.