Semiconductor memory device and manufacturing method thereof

Abstract

A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a plurality of insulating layers spaced apart from each other in a stacking direction, a slit insulating layer passing through the plurality of insulating layers, a plurality of first variable resistance layers alternately disposed with the plurality of insulating layers in the stacking direction, a plurality of conductive lines interposed between the slit insulating layer and the plurality of first variable resistance layers and alternately disposed with the plurality of insulating layers in the stacking direction, a conductive pillar passing through the plurality of insulating layers and the plurality of first variable resistance layers, and a second variable resistance layer surrounding a sidewall of the conductive pillar.

What is claimed is: 
     
         1 . A semiconductor memory device, comprising:
 a plurality of insulating layers spaced apart from each other in a stacking direction;   a slit insulating layer passing through the plurality of insulating layers;   a plurality of first variable resistance layers alternately disposed with the plurality of insulating layers in the stacking direction;   a plurality of conductive lines interposed between the slit insulating layer and the plurality of first variable resistance layers and alternately disposed with the plurality of insulating layers in the stacking direction;   a conductive pillar passing through the plurality of insulating layers and the plurality of first variable resistance layers; and   a second variable resistance layer surrounding a sidewall of the conductive pillar,   wherein the plurality of first variable resistance layers and the second variable resistance layer include a material of which threshold voltage varies depending on polarity of a program pulse.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein each of the plurality of first variable resistance layers includes a first etched surface facing the conductive pillar. 
     
     
         3 . The semiconductor memory device of  claim 1 , wherein the plurality of first variable resistance layers include a chalcogenide material having substantially the same composition as a chalcogenide material of the second variable resistance layer. 
     
     
         4 . The semiconductor memory device of  claim 1 , wherein the second variable resistance layer includes one or more elements that constitute each of the plurality of first variable resistance layers. 
     
     
         5 . The semiconductor memory device of  claim 1 , wherein each of the plurality of first variable resistance layers and the second variable resistance layer include germanium (Ge) and selenium (Se). 
     
     
         6 . The semiconductor memory device of  claim 5 , wherein the second variable resistance layer includes a material of which content of at least one of germanium (Ge) and selenium (Se) is higher than content of at least one of germanium (Ge) and selenium (Se) of a material in each of the plurality of first variable resistance layers. 
     
     
         7 . The semiconductor memory device of  claim 1 , further comprising a plurality of third variable resistance layers alternately disposed with the plurality of insulating layers in the stacking direction and interposed between the plurality of first variable resistance layers and the plurality of conductive lines. 
     
     
         8 . The semiconductor memory device of  claim 7 , wherein each of the plurality of first variable resistance layers includes a second etched surface facing a corresponding conductive line among the plurality of conductive lines. 
     
     
         9 . The semiconductor memory device of  claim 7 , wherein the plurality of third variable resistance layers include a material of which threshold voltage varies depending on the polarity of the program pulse. 
     
     
         10 . The semiconductor memory device of  claim 7 , wherein the plurality of first variable resistance layers may include a chalcogenide material having substantially the same composition as a chalcogenide material of the plurality of third variable resistance layers. 
     
     
         11 . The semiconductor memory device of  claim 7 , wherein each of the plurality of third variable resistance layers includes one or more elements that constitute each of the plurality of first variable resistance layers. 
     
     
         12 . The semiconductor memory device of  claim 7 , wherein each of the plurality of first variable resistance layers and each of the plurality of third variable resistance layers include germanium (Ge) and selenium (Se). 
     
     
         13 . The semiconductor memory device of  claim 12 , wherein each of the plurality of third variable resistance layers includes a material of which content of at least one of germanium (Ge) and selenium (Se) is higher than content of at least one of germanium (Ge) and selenium (Se) of a material in each of the plurality of first variable resistance layers. 
     
     
         14 . A method of manufacturing a semiconductor memory device, the method comprising:
 forming a stacked structure including a plurality of insulating layers and a plurality of first variable resistance layers that are alternately stacked with each other;   forming a hole passing through the stacked structure;   forming a second variable resistance layer on a sidewall of the hole;   forming a conductive pillar in a region of the hole that is exposed by the second variable resistance layer;   forming a slit passing through the stacked structure;   forming a plurality of openings by etching a part of each of the plurality of first variable resistance layers, the part being adjacent to the slit; and   forming a plurality of conductive lines respectively in the plurality of openings.   
     
     
         15 . The method of  claim 14 , wherein the second variable resistance layer contacts the plurality of first variable resistance layers. 
     
     
         16 . The method of  claim 14 , wherein each of the plurality of first variable resistance layers includes germanium (Ge) and selenium (Se), and
 wherein the second variable resistance layer includes a material of which content of at least one of germanium (Ge) and selenium (Se) is higher than content of at least one of germanium (Ge) and selenium (Se) of a material in each of the plurality of first variable resistance layers, when the second variable resistance layer is formed.   
     
     
         17 . The method of  claim 14 , further comprising forming a plurality of third variable resistance layers respectively in the plurality of openings,
 wherein the plurality of conductive lines are formed respectively in the plurality of openings after forming the plurality of third variable resistance layers.   
     
     
         18 . The method of  claim 17 , wherein the plurality of third variable resistance layers respectively contact the plurality of first variable resistance layers. 
     
     
         19 . The method of  claim 17 , wherein each of the plurality of first variable resistance layers includes germanium (Ge) and selenium (Se), and
 wherein the plurality of third variable resistance layers include a material of which content of at least one of germanium (Ge) and selenium (Se) is higher than content of at least one of germanium (Ge) and selenium (Se) of a material in each of the plurality of first variable resistance layers, when the plurality of third variable resistance layers are formed.