Method of forming pairs of three-gate non-volatile flash memory cells using two polysilicon deposition steps

Abstract

A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

What is claimed is: 
     
         1 . A method of forming a pair of non-volatile memory cells comprising:
 forming a first insulation layer on a semiconductor substrate;   forming a first polysilicon layer on the first insulation layer in a first polysilicon deposition process;   forming an insulation block on the first polysilicon layer having opposing first and second sides;   forming a first insulation spacer on the first polysilicon layer and adjacent the first side and a second insulation spacer on the first polysilicon layer and adjacent the second side;   removing portions of the first polysilicon layer while maintaining a polysilicon block of the first polysilicon layer disposed under the insulation block and first and second insulation spacers;   removing the insulation block;   removing a portion of the first polysilicon layer disposed between the first and second insulation spacers to form a first polysilicon block of the first polysilicon layer disposed under the first insulation spacer and a second polysilicon block of the first polysilicon layer disposed under the second insulation spacer;   forming a source region in the substrate and between the first and second insulation spacers;   forming insulation material that at least extends along an end portion of each of the first and second polysilicon blocks of the first polysilicon layer;   forming a second polysilicon layer over the substrate and the pair of insulation spacers in a second polysilicon deposition process;   removing portions of the second polysilicon layer while maintaining a third polysilicon block, a fourth polysilicon block and a fifth polysilicon block of the second polysilicon layer, wherein:
 the third polysilicon block is disposed between the pair of insulation spacers and over the source region, 
 the fourth polysilicon block is disposed adjacent the first insulation spacer, and 
 the fifth polysilicon block is disposed adjacent the second insulation spacer; 
   forming a first drain region in the substrate and adjacent the fourth polysilicon block; and   forming a second drain region in the substrate and adjacent the fifth polysilicon block.   
     
     
         2 . The method of  claim 1 , wherein before the removal of the insulation block, further comprising:
 performing a poly slope etch to an upper surface of the first polysilicon layer such the upper surface slopes downwardly as the upper surface extends away from the insulation block.   
     
     
         3 . The method of  claim 1 , wherein the third polysilicon block includes a first portion laterally adjacent to the first and second polysilicon blocks of the first polysilicon layer, and a second portion that extends up and over the first and second polysilicon blocks of the first polysilicon layer. 
     
     
         4 . The method of  claim 1 , wherein the insulation block is formed of nitride, oxide, or a composite of layers including both oxide and nitride. 
     
     
         5 . The method of  claim 1 , wherein the first insulation layer is formed of oxide or nitrogen treated oxide. 
     
     
         6 . The method of  claim 1 , further comprising:
 removing the fourth and fifth polysilicon blocks; and   forming a first metal block adjacent the first insulation spacer;   forming a second metal block adjacent the second insulation spacer.   
     
     
         7 . The method of  claim 6 , further comprising:
 forming a layer of high-K insulation material between the first metal block and the first insulation spacer; and   forming a layer of high-K insulation material between the second metal block and the second insulation spacer.