Accessing stored metadata to identify memory devices in which data is stored

Abstract

A computer system stores metadata that is used to identify physical memory devices that store randomly-accessible data for memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. Stored metadata associates a first address range of the address space with a first memory device, and a second address range of the address space with a second memory device. The operating system manages processes running on the computer system by accessing the stored metadata. This management includes allocating memory based on the stored metadata so that data for a first process is stored in the first memory device, and data for a second process is stored in the second memory device.

What is claimed is: 
     
         1 . A system comprising:
 a first memory device;   a second memory device;   at least one processing device; and   memory containing instructions configured to instruct the at least one processing device to:
 access memory in an address space maintained by an operating system, the accessing including accessing the first memory device and the second memory device using addresses in the address space; 
 store metadata that associates a first address range of the address space with the first memory device, and a second address range of the address space with the second memory device; and 
 manage, by the operating system based on the stored metadata, processes including a first process and a second process, wherein data for the first process is stored in the first memory device, and data for the second process is stored in the second memory device. 
   
     
     
         2 . The system of  claim 1 , wherein the first process has a first priority, the second process has a second priority, and the first memory device is selected to store the data for the first process in response to determining that the first priority is higher than the second priority. 
     
     
         3 . The system of  claim 1 , wherein:
 the first process corresponds to a first application;   the instructions are further configured to instruct the at least one processing device to receive a request from the first application that indicates a type of memory to use for storing data; and   the first memory device is selected to store the data for the first process based on the indicated type of memory.   
     
     
         4 . The system of  claim 1 , further comprising a buffer to store the metadata, wherein the operating system receives a virtual address in the first address range from the first process, and accesses the buffer to determine a physical address of the first memory device corresponding to the virtual address. 
     
     
         5 . The system of  claim 1 , wherein a read latency of the first memory device is less than a read latency of the second memory device, and wherein the instructions are further configured to instruct the at least one processing device to store the metadata in the first memory device. 
     
     
         6 . The system of  claim 1 , further comprising a memory management unit configured to, when accessing the stored data for the first process, map a virtual address in the first address range to a physical address in the first memory device. 
     
     
         7 . An apparatus comprising:
 a memory module comprising a host interface configured to receive commands from a host operating system;   a memory bus; and   a processing device configured to run the host operating system, wherein the host operating system accesses the memory module using the memory bus and includes at least one first device driver that provides memory services using the memory module, and wherein the first device driver maps pages of data stored in DRAM and NAND flash memory.   
     
     
         8 . The apparatus of  claim 7 , wherein the host operating system comprises a hypervisor configured to provision a virtual machine. 
     
     
         9 . The apparatus of  claim 8 , wherein the virtual machine allows a guest operating system to provide resources to applications running in the guest operating system. 
     
     
         10 . The apparatus of  claim 7 , wherein the host operating system comprises a hypervisor configured to provision virtual memory that uses at least a portion of memory in the memory module. 
     
     
         11 . The apparatus of  claim 7 , wherein a second device driver of a guest operating system is configured to communicate with the first device driver for memory ballooning when additional capacity in the DRAM or NAND flash memory is available. 
     
     
         12 . The apparatus of  claim 7 , wherein the first device driver is configured to request page-in of a page from slower memory to faster memory. 
     
     
         13 . The apparatus of  claim 12 , wherein the slower memory includes the NAND flash memory, and the faster memory includes the DRAM. 
     
     
         14 . The apparatus of  claim 12 , wherein the processing device is further configured to move the page from slower memory to faster memory based on address range data stored as metadata in the memory module. 
     
     
         15 . A system comprising:
 a memory controller configured to communicate with a host and to manage data based on stored metadata;   volatile memory;   non-volatile memory; and   a multiplexer controlled by the controller and configured to selectively store data in either the volatile memory or non-volatile memory based on the stored metadata.   
     
     
         16 . The system of  claim 15 , wherein the multiplexer is controlled based on signals received from the memory controller in response to receiving read or write commands from the host. 
     
     
         17 . The system of  claim 15 , wherein the memory controller is further configured to provide the host with access to any address in the volatile memory and the non-volatile memory using a memory protocol. 
     
     
         18 . The system of  claim 17 , wherein the memory protocol uses double data rate timing. 
     
     
         19 . The system of  claim 15 , wherein the non-volatile memory is NVRAM. 
     
     
         20 . The system of  claim 15 , wherein the memory controller is further configured to provide a page-in/out control path for the host to request a page in the volatile memory or the non-volatile memory.