Surging flow for bubble clearing in electroplating systems

Abstract

Exemplary methods of semiconductor processing may include performing an electroplating operation on a semiconductor substrate in an electroplating bath within a vessel of an electroplating system. The methods may include removing the semiconductor substrate from the electroplating bath. The methods may include closing a valve associated with a first drain from the electroplating system. The methods may include increasing flow to a second drain from the electroplating system. The second drain may be associated with a drain channel from the vessel of the electroplating system.

What is claimed is: 
     
         1 . A method of semiconductor processing comprising:
 performing an electroplating operation on a semiconductor substrate in an electroplating bath within a vessel of an electroplating system;   removing the semiconductor substrate from the electroplating bath;   closing a valve associated with a first drain from the electroplating system; and   increasing flow to a second drain from the electroplating system, wherein the second drain is associated with a drain channel from the vessel of the electroplating system.   
     
     
         2 . The method of semiconductor processing of  claim 1 , wherein the vessel comprises a weir about the vessel, and wherein increasing flow to the second drain increases flow over the weir into the drain channel providing access to the second drain. 
     
     
         3 . The method of semiconductor processing of  claim 2 , wherein the weir defines a plurality of notches extending from an upper surface of the weir. 
     
     
         4 . The method of semiconductor processing of  claim 1 , wherein the vessel includes an upper cup defining a plurality of channels through an upper surface of the upper cup, and wherein one or more apertures couples each channel of the plurality of channels with a volume within the vessel in fluid contact with a membrane. 
     
     
         5 . The method of semiconductor processing of  claim 4 , wherein a catholyte is flowed within the volume, and wherein the volume is in contact with a first surface of the membrane. 
     
     
         6 . The method of semiconductor processing of  claim 5 , further comprising:
 flowing an anolyte in contact with a second surface of the membrane opposite the first surface of the membrane.   
     
     
         7 . The method of semiconductor processing of  claim 5 , wherein the first drain is associated with one or more outlets of the volume within the vessel. 
     
     
         8 . The method of semiconductor processing of  claim 5 , wherein a central channel is defined through the upper cup, wherein catholyte is flowed into the vessel through the upper cup, and wherein, while performing the electroplating operation, catholyte flow extends both into each channel of the plurality of channels and over a weir extending about the vessel. 
     
     
         9 . The method of semiconductor processing of  claim 1 , wherein the electroplating system further comprises:
 a return pump fluidly coupled with the second drain; and   a level sensor disposed within the drain channel, wherein the level sensor is communicatively coupled with the return pump.   
     
     
         10 . The method of semiconductor processing of  claim 9 , wherein the return pump is operable to increase a flow rate from the second drain in response to a signal from the level sensor indicating an increase in catholyte level within the drain channel. 
     
     
         11 . A method of semiconductor processing comprising:
 performing an electroplating operation on a semiconductor substrate in an electroplating bath within a vessel of an electroplating system;   removing the semiconductor substrate from the electroplating bath;   diverting flow to a first drain from the electroplating system;   increasing flow to a second drain from the electroplating system, wherein the second drain is associated with a drain channel from the vessel of the electroplating system, wherein increasing flow to the second drain occurs for a first period of time; and   reducing flow to the second drain from the electroplating system after the first period of time.   
     
     
         12 . The method of semiconductor processing of  claim 11 , further comprising, while reducing flow to the second drain after the first period of time:
 increasing flow to the first drain.   
     
     
         13 . The method of semiconductor processing of  claim 11 , wherein the vessel comprises a weir about the vessel, and wherein increasing flow to the second drain increases flow over the weir into the drain channel providing access to the second drain. 
     
     
         14 . The method of operating an electroplating system of  claim 13 , wherein the weir defines a plurality of notches extending from an upper surface of the weir. 
     
     
         15 . The method of operating an electroplating system of  claim 13 , wherein the vessel includes an upper cup defining a plurality of channels through an upper surface of the upper cup, and wherein one or more apertures couples each channel of the plurality of channels with a volume within the vessel in fluid contact with a membrane. 
     
     
         16 . The method of operating an electroplating system of  claim 15 , wherein a central channel is defined through the upper cup, wherein catholyte is flowed into the vessel through the upper cup, and wherein, while performing the electroplating operation, catholyte flow extends both into each channel of the plurality of channels and over the weir. 
     
     
         17 . The method of semiconductor processing of  claim 11 , wherein, while increasing flow to the second drain, a height of catholyte increases within the drain channel by less than or about 2 cm. 
     
     
         18 . The method of semiconductor processing of  claim 11 , wherein the first period of time is less than or about 30 seconds. 
     
     
         19 . A method of semiconductor processing comprising:
 performing an electroplating operation on a semiconductor substrate in an electroplating bath within a vessel of an electroplating system, wherein the vessel comprises a weir about the vessel;   removing the semiconductor substrate from the electroplating bath;   providing a first flow through the electroplating system through a central channel through the vessel; and   providing a second flow through the electroplating system through secondary channels through the vessel and radially outward of the central channel, wherein the first flow and the second flow extend to a drain channel from the vessel of the electroplating system, and wherein the flow to the drain channel extends over the weir into the drain channel, which provides access to a drain.   
     
     
         20 . The method of semiconductor processing of  claim 19 , wherein the weir defines a plurality of notches extending from an upper surface of the weir, and wherein, while increasing flow to the second drain, a height of catholyte within the drain channel increases by less than or about 2 cm.