Resilient storage circuits

Abstract

The present disclosure includes an integrated circuit comprising a first pair of complementary transistors configured in series, a second pair of complementary transistors configured in series, and at least one charge extraction transistor having a gate coupled to a first potential, a source coupled to a second potential, and a drain coupled to a data storage node of one of the first or second pairs of complementary transistors. The first potential and second potential bias the at least one charge extraction transistor in a nonconductive state. The drain of the at least one charge extraction transistor is formed in a doped material shared with a drain of a transistor of the first or second pairs of complementary transistors.

What is claimed is: 
     
         1 . An integrated circuit comprising:
 a first pair of complementary transistors configured in series;   a second pair of complementary transistors configured in series;   at least one charge extraction transistor having a gate coupled to a first potential, a source coupled to a second potential, and a drain coupled to a data storage node of one of the first or second pairs of complementary transistors, wherein the first potential and second potential bias the at least one charge extraction transistor in a nonconductive state; and   wherein the drain of the at least one charge extraction transistor is formed in a doped material shared with a drain of a transistor of the first or second pairs of complementary transistors.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the at least one charge extraction transistor has a same device type as said transistor of the first or second pairs of complementary transistors. 
     
     
         3 . The integrated circuit of  claim 1 , wherein the first charge extraction transistor is a N-type transistor formed in a P-well and said transistor of the first or second pairs of complementary transistors is a N-type transistor. 
     
     
         4 . The integrated circuit of  claim 1 , wherein the first charge extraction transistor is a P-type transistor formed in a N-well said transistor of the first or second pairs of complementary transistors is a P-type transistor. 
     
     
         5 . The integrated circuit of  claim 1 , wherein the at least one charge extraction transistor is a N-type transistor configured in a same P-well as a N-type transistor of the first pair of complementary transistors, and further comprising a P-type charge extraction transistor formed in a doped material shared with a drain of a P-type transistor configured in a same N-well of the first pair of complementary transistors, wherein the P-type charge extraction transistor has a gate coupled to the second potential, a source coupled to the first potential, and a drain coupled to the data storage node, wherein the first potential and second potential bias the P-type charge extraction transistor charge extraction transistor in a nonconductive state. 
     
     
         6 . The integrated circuit of  claim 1 , wherein the first pair of complementary transistors are further configured in series with one or more transistors configured to receive a clock signal. 
     
     
         7 . The integrated circuit of  claim 1 , wherein the second pair of complementary transistors are further configured in series with one or more transistors configured to receive a reset signal. 
     
     
         8 . The integrated circuit of  claim 1 , wherein gates of the first pair of complementary transistors are coupled together, gates of the second pair of complementary transistors are coupled together, a first data storage node of the first pair of complementary transistors is coupled to the gates of the second pair of complementary transistors, and a second data storage node of the second pair of complementary transistors is coupled to the gates of the first pair of complementary transistors. 
     
     
         9 . The integrated circuit of  claim 1 , wherein:
 the first pair of complementary transistors comprise a first N-type transistor formed in a first P-type material and a first P-type transistor formed in a first N-type material,   the second pair of complementary transistors comprise a second N-type transistor formed in a second P-type material and a second P-type transistor formed in a second N-type material, and   wherein the first and second N-type transistors are formed in different P-wells and the first and second P-type transistors are formed in different N-wells.   
     
     
         10 . An integrated circuit comprising:
 a first pair of complementary transistors configured in series;   a second pair of complementary transistors configured in series; and   charge extraction means, coupled to a data storage node of one of the first or second pairs of complementary transistors, for removing charge generated by a transient, and in accordance therewith, prevent a state of the data storage node from changing.   
     
     
         11 . The integrated circuit of  claim 10 , wherein the charge extraction means is formed in a doped material shared with a drain of a transistor of the first or second pairs of complementary transistors. 
     
     
         12 . The integrated circuit of  claim 10 , wherein the charge extraction means is coupled to one or more potentials to bias the charge extraction means in a nonconductive state. 
     
     
         13 . The integrated circuit of  claim 12 , wherein the one or more potentials comprise a first potential coupled to a first terminal of the charge extraction means and a second potential coupled to a second terminal of the charge extraction means, wherein the first potential and second potential bias the charge extraction means in a nonconductive state. 
     
     
         14 . The integrated circuit of  claim 10 , wherein a terminal of the charge extraction means is formed in a doped material shared with a drain of a transistor of the first or second pairs of complementary transistors. 
     
     
         15 . The integrated circuit of  claim 14 , wherein the charge extraction means comprises a N-type transistor formed in a P-well and said transistor of the first or second pairs of complementary transistors is a N-type transistor. 
     
     
         16 . The integrated circuit of  claim 14 , wherein the charge extraction means comprises a P-type transistor formed in a N-well and said transistor of the first or second pairs of complementary transistors is a P-type transistor.