Extreme ultra-violet (euv) lithography processes for patterning photoresist and photolithography masks used therein

Abstract

An extreme ultra-violet (EUV) lithography process includes lithographically patterning first through fourth photoresist regions on respective first through fourth regions of a semiconductor substrate, in sequence, using a mask. This mask includes a main area in which a main pattern is defined, a first dummy area in which a first dummy pattern is defined, a second dummy area in which a plurality of second sub-dummy patterns are defined at corresponding corners of the mask, and an alignment area including an alignment pattern therein that is spaced farther from a center of the main area relative to the first and second dummy areas. During the lithographically patterning, at least part of the alignment area on the first region of the substrate is exposed at least three times to EUV light, using the mask.

1 . A lithography process, comprising:
 lithographically patterning first through fourth photoresist regions on respective first through fourth regions of a semiconductor substrate, in sequence, using a mask comprising:
 a main area in which a main pattern is defined; 
 a first dummy area in which a first dummy pattern is defined, said first dummy area at least partially surrounding the main area; and 
 a second dummy area in which a plurality of second sub-dummy patterns are defined at corresponding corners of the mask that are spaced apart from the first dummy area; and 
   wherein said lithographically patterning the first through fourth photoresist regions comprises exposing at least part of the second dummy area on the first region of the substrate at least three times using the mask.   
     
     
         2 . The lithography process of  claim 1 , wherein a width of the second sub-dummy patterns is greater than a width of the first dummy pattern; wherein the main pattern includes a main gate pattern; wherein the second dummy pattern includes a second dummy gate pattern; and wherein a width of the second dummy gate pattern is greater than a width of the main gate pattern. 
     
     
         3 . The lithography process of  claim 2 , wherein the width of the main gate pattern is in a range from 1 nm to 90 nm. 
     
     
         4 . The lithography process of  claim 2 , wherein the width of the second dummy gate pattern is in a range from 100 nm to 150 nm. 
     
     
         5 . The lithography process of  claim 1 , wherein the main pattern includes a main active pattern; wherein the second dummy pattern includes a second dummy active pattern; and wherein a width of the second dummy active pattern is greater than a width of the main active pattern. 
     
     
         6 . The lithography process of  claim 1 , wherein a width of the second dummy area is in a range from 7 μm to 10 μm. 
     
     
         7 . The lithography process of  claim 1 , wherein a size of the second dummy area is in a range of 49 μm 2  to 100 μm 2 . 
     
     
         8 . The lithography process of  claim 1 , wherein the mask includes first to fourth areas arranged in a first direction; wherein each of the first to fourth areas extends in a second direction intersecting the first direction; wherein the first area entirely overlaps the second area in the first direction; wherein a portion of the third area protrudes, in the second direction, from an end of the second area; and wherein the fourth area entirely overlaps the third area in the first direction. 
     
     
         9 . The lithography process of  claim 8 , wherein the second sub-dummy patterns are respectively disposed in a first corner of the first area, a second corner of the second area, a fourth corner of the second area, and a third corner of the third area, but not in the fourth area. 
     
     
         10 . The lithography process of  claim 8 , wherein the second dummy area is not disposed in: a boundary area between the first area and the second area, a boundary area between the second area and the third area, and a boundary area between the third area and the fourth area. 
     
     
         11 . An extreme ultra-violet (EUV) lithography process, comprising:
 lithographically patterning first through fourth photoresist regions on respective first through fourth regions of a semiconductor substrate, in sequence, using a mask comprising:
 a main area in which a main pattern is defined; 
 a first dummy area in which a first dummy pattern is defined, said first dummy area at least partially surrounding the main area; 
 a second dummy area in which a plurality of second sub-dummy patterns are defined at corresponding corners of the mask that are spaced apart from the first dummy area; and 
 an alignment area including an alignment pattern therein that is spaced farther from a center of the main area relative to the first and second dummy areas; and 
   wherein said lithographically patterning the first through fourth photoresist regions comprises exposing at least part of the alignment area on the first region of the substrate at least three times to EUV light, using the mask.   
     
     
         12 . The lithography process of  claim 11 , wherein a perimeter of the mask is generally rectangular-shaped, but with three square-shaped cutouts at first, second and third corners of the mask; and wherein the alignment area extends as a protrusion from the fourth corner of the mask. 
     
     
         13 . The lithography process of  claim 12 , wherein the alignment pattern is in the shape of a cross sign. 
     
     
         14 . The lithography process of  claim 13 , wherein a center of the alignment pattern is aligned to: (i) a first side of the mask extending in a first direction, and (ii) a second side of the mask extending in a second direction orthogonal to the first direction. 
     
     
         15 . An extreme ultra-violet (EUV) lithography process, comprising:
 lithographically patterning first through fourth photoresist regions on respective first through fourth regions of a semiconductor substrate, in sequence, using a mask having a generally rectangular-shaped perimeter, but with three square-shaped cutouts at first, second and third corners of the mask, and an alignment area that extends as a protrusion from the fourth corner of the mask.   
     
     
         16 . The lithography process of  claim 15 , wherein a portion of the photoresist on the first region of the semiconductor substrate is exposed at least three times to EUV light during said lithographically patterning. 
     
     
         17 . The lithography process of  claim 16 , wherein the alignment area includes a cross-shaped alignment pattern therein. 
     
     
         18 . The lithography process of  claim 17 , wherein a center of the alignment pattern is aligned to: (i) a first side of the mask extending in a first direction, and (ii) a second side of the mask extending in a second direction orthogonal to the first direction. 
     
     
         19 . The lithography process of  claim 16 , wherein the mask includes a plurality of dummy patterns extending between first and second ones of the square- shaped cutouts. 
     
     
         20 . The lithography process of  claim 19 , wherein the mask includes a plurality of dummy patterns extending between a third one of the square-shaped cutouts and the alignment area. 
     
     
         21 .- 40 . (canceled)