Charge pump circuit and method

Abstract

A charge pump circuit includes an output stage coupled to an output, a pumping stage between an input and the output stage, and a control circuit that outputs control signals. A pumping stage transistor includes S/D terminals coupled to input/output terminals, capacitive devices between signal terminals and either a transistor gate or a S/D terminal, and diode devices including either the anode/cathode or cathode/anode coupled to the respective gate and S/D terminal. An output stage transistor includes S/D terminals coupled to an input terminal and the output. One control signal includes a transition from first to second logic levels at a first time and another control signal includes a transition from the first to second logic levels at a second time, and a period between the transitions is sufficiently small to cause a change in a voltage at the pumping stage S/D terminal to be less than 100 millivolts.

What is claimed is: 
     
         1 . A charge pump circuit, comprising:
 input and output nodes;   an output stage circuit coupled to the output node;   a pumping stage circuit coupled between the input node and the output stage circuit; and   a control circuit configured to output first and second control signals to respective first and second control signal terminals of the pumping stage circuit;   wherein   the pumping stage circuit comprises:
 a first input terminal; 
 an output terminal; 
 a first transistor comprising a first source/drain (S/D) terminal coupled to the first input terminal, a second S/D terminal coupled to the output terminal, and a first gate terminal; 
 a first capacitive device coupled between the first control signal terminal and the first gate terminal; 
 a second capacitive device coupled between the second control signal terminal and the second S/D terminal; 
 a first diode device comprising a first anode coupled to the first gate terminal and a first cathode coupled to the second S/D terminal; and 
 a second diode device comprising a second cathode coupled to the first gate terminal and a second anode coupled to the second S/D terminal, the output stage circuit comprises: 
 a second input terminal; and 
 a second transistor comprising a third S/D terminal coupled to the second input terminal and a fourth S/D terminal coupled to the output node, 
   the control circuit is configured to generate the first control signal comprising a first transition from a first logic level to a second logic level at a first time and the second control signal comprising a second transition from the first logic level to the second logic level at a second time, and   a time period between the first and second transitions is sufficiently small to cause a change in a voltage at the second S/D terminal of the first transistor from the first time to the second time to be less than 100 millivolts.   
     
     
         2 . The charge pump circuit of  claim 1 , wherein
 the control circuit is configured to generate the second control signal comprising a third transition from the second logic level to the first logic level at a third time and the first control signal comprising a fourth transition from the second logic level to the first logic level at a fourth time, and   another time period between the third and fourth transitions is sufficiently small to cause another change in the voltage at the second S/D terminal of the first transistor from the third time to the fourth time to be less than 100 millivolts.   
     
     
         3 . The charge pump circuit of  claim 1 , wherein a forward bias voltage drop of the first diode device is greater than a forward bias voltage drop of the second diode device. 
     
     
         4 . The charge pump circuit of  claim 1 , wherein a forward bias voltage drop of the first diode device is greater than a threshold voltage of the first transistor. 
     
     
         5 . The charge pump circuit of  claim 1 , wherein a forward bias voltage drop of the first diode device is less than a voltage difference between the first and second logic levels. 
     
     
         6 . The charge pump circuit of  claim 1 , wherein one or both of the first or second diode devices comprises a plurality of diode-connected transistors coupled in series. 
     
     
         7 . The charge pump circuit of  claim 1 , wherein the pumping stage circuit further comprises:
 a first driver coupled between the first control signal terminal and the first capacitive device; and   a second driver coupled between the second control signal terminal and the second capacitive device.   
     
     
         8 . The charge pump circuit of  claim 1 , wherein the output stage circuit further comprises:
 a third control signal terminal configured to receive the first control signal;   a third capacitive device coupled between the third control signal terminal and a second gate terminal of the second transistor;   a fourth capacitive device coupled between the output node and a supply reference terminal configured to have a voltage level the same as the logic low level;   a third diode device comprising a third anode coupled to the second gate terminal and a third cathode coupled to the fourth S/D terminal; and   a fourth diode device comprising a fourth cathode coupled to the second gate terminal and a fourth anode coupled to the fourth S/D terminal.   
     
     
         9 . A charge pump circuit, comprising:
 input and output nodes;   a control circuit configured to output first and second control signals;   a pumping stage circuit and an output stage circuit coupled in series between the input and output nodes, wherein each of the pumping stage and output stage circuits comprises:
 input and output terminals; 
 first and second diode devices; 
 a transistor comprising:
 a first source/drain (S/D) terminal coupled to the input terminal; 
 a second S/D terminal coupled to the output terminal, a cathode of the first diode device, and an anode of the second diode device; and 
 a gate terminal coupled to an anode of the first diode device and a cathode of the second diode device; 
 
 a first driver configured to output a first driving signal based on the first control signal; 
 a first capacitive device coupled to the first driver and the gate terminal; and 
 a second capacitive device coupled to the output terminal, 
   wherein   the pumping stage circuit further comprises a second driver coupled to the second capacitive device and configured to output a second driving signal based on the second control signal,   the control circuit is configured to generate the first control signal comprising a first transition from a first logic level to a second logic level at a first time and the second control signal comprising a second transition from the first logic level to the second logic level at a second time, and   a time period between the first and second transitions is sufficiently small to cause a change in a voltage at the gate or second S/D terminal of the pumping stage circuit transistor from the first time to the second time to be less than 100 millivolts.   
     
     
         10 . The charge pump circuit of  claim 9 , wherein
 the control circuit is configured to generate the second control signal comprising a third transition from the second logic level to the first logic level at a third time and the first control signal comprising a fourth transition from the second logic level to the first logic level at a fourth time, and   another time period between the third and fourth transitions is sufficiently small to cause another change in the voltage at the gate or second S/D terminal of the pumping stage circuit transistor from the third time to the fourth time to be less than 100 millivolts.   
     
     
         11 . The charge pump circuit of  claim 9 , wherein one or more of the first or second driver of the pumping stage circuit or the first driver of the output stage circuit comprises an inverter, a buffer, or a level shifter. 
     
     
         12 . The charge pump circuit of  claim 9 , wherein
 the control circuit is configured to generate the first control signal and the first driver is configured to output the first driving signal each having a first voltage level corresponding to the first or second logic level being a logic high level,   the control circuit is configured to generate the second control signal and the second driver is configured to output the second driving signal each having a second voltage level corresponding to the first or second logic level being the logic high level, and   the first voltage level is greater than the second voltage level.   
     
     
         13 . The charge pump circuit of  claim 9 , wherein
 the control circuit is configured to generate each of the first and second control signals having a first voltage level corresponding to the first or second logic level being a logic high level,   the first and second drivers are configured to output each of the respective first and second driving signals having a second voltage level corresponding to the first or second logic level being the logic high level, and   the first voltage level is greater than the second voltage level.   
     
     
         14 . The charge pump circuit of  claim 9 , wherein a forward bias voltage drop of the first diode device is greater than a forward bias voltage drop of the second diode device. 
     
     
         15 . The charge pump circuit of  claim 9 , wherein the control circuit comprises a two-phase, non-overlapping clock generator configured to generate the first and second control signals. 
     
     
         16 . The charge pump circuit of  claim 9 , wherein the second capacitive device of the output stage circuit is coupled to a supply reference terminal configured to have a reference ground voltage level. 
     
     
         17 . A method of operating a charge pump circuit, the method comprising:
 generating a first transition in a first control signal from a first predetermined voltage level to a second predetermined voltage level at a first time;   generating a second transition in a second control signal from the first predetermined voltage level to the second predetermined voltage level at a second time;   operating a pumping stage circuit of the charge pump circuit by:
 causing a first voltage at a first end of a first capacitive device to transition from a first voltage level to a second voltage level responsive to the first transition in the first control signal, the first end of the first capacitive device being electrically coupled to a gate terminal of a first transistor; and 
 causing a second voltage at a second end of a second capacitive device to transition from a third voltage level to a fourth voltage level responsive to the second transition in the second control signal, the second end of the second capacitive device being electrically coupled to a source/drain (S/D) terminal of the first transistor, wherein
 a first diode device comprises a first anode coupled to the gate terminal of the first transistor and a first cathode connected to the S/D terminal of the transistor, and 
 a second diode device comprises a second cathode coupled to the gate terminal of the first transistor and a second anode connected to the S/D terminal of the transistor; and 
 
   operating a pumping stage circuit of the charge pump circuit by generating an output voltage based on an output of the pumping stage circuit,   wherein a time period between the first and second transitions is sufficiently small to cause a change in a voltage at the S/D terminal of the transistor from the first time to the second time to be less than 100 millivolts.   
     
     
         18 . The method of  claim 17 , further comprising:
 generating a third transition in the second control signal from the second predetermined voltage level to the first predetermined voltage level at a third time; and   generating a fourth transition in the first control signal from the second predetermined voltage level to the first predetermined voltage level at a fourth time,   wherein another time period between the third and fourth transitions is sufficiently small to cause another change in the voltage at the S/D terminal of the transistor from the first time to the second time to be less than 100 millivolts.   
     
     
         19 . The method of  claim 17 , wherein
 the causing the first voltage at the first end of the first capacitive device to transition from the first voltage level to the second voltage level comprises outputting a first driving signal from a first inverter responsive to the first transition in the first control signal, and   the causing the second voltage at the second end of the second capacitive device to transition from the third voltage level to the fourth voltage level comprises outputting a second driving signal from a second inverter responsive to the second transition in the second control signal.   
     
     
         20 . The method of  claim 19 , wherein
 the generating each of the first transition in the first control signal and the second transition in the second control signal comprises generating one of the first or second predetermined voltage levels corresponding to a logic high level,   the outputting each of the first and second driving signals comprises outputting a third predetermined voltage level corresponding to the logic high level, and   the one of the first or second predetermined voltage levels corresponding to the logic high level is greater than the third predetermined voltage level.