Instruction packing scheme for vliw cpu architecture

Abstract

A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.

What is claimed is: 
     
         1 . A method comprising:
 receiving a first packet that includes:
 a first instruction that includes a first primary opcode portion; and 
 a second instruction that includes:
 a second primary opcode portion arranged adjacent to the first primary opcode portion in the first packet; and 
 a secondary opcode portion separated from the second primary opcode portion in the first packet; 
 
   determining a first functional unit associated with the first instruction based on the first primary opcode portion;   providing a second packet that includes the first primary opcode portion to the first functional unit;   determining a second functional unit associated with the second instruction based on the second primary opcode portion; and   providing a third packet that includes the second primary opcode portion and the secondary opcode portion to the second functional unit.   
     
     
         2 . The method of  claim 1 , wherein:
 the first instruction includes a first size field that specifies a size of the first instruction based on the first size field and the first primary opcode portion; and   the second instruction includes a second size field that specifies a size of the second instruction based on the second size field, the second primary opcode portion, and the secondary opcode portion.   
     
     
         3 . The method of  claim 2 , wherein the size of the first instruction is different from the size of the second instruction. 
     
     
         4 . The method of  claim 2 , wherein:
 the first instruction includes a first link field that specifies whether the first instruction is last in the first packet;   the size of the first instruction as specified by the first size field is further based on the first link field;   the second instruction includes a second link field that specifies whether the second instruction is last in the first packet; and   the size of the second instruction as specified by the second size field is further based on the second link field.   
     
     
         5 . The method of  claim 1 , wherein a size of the first primary opcode portion is equal to a size of the second primary opcode portion. 
     
     
         6 . The method of  claim 1 , wherein the first instruction does not include a secondary opcode portion. 
     
     
         7 . The method of  claim 1 , wherein the determining of the first functional unit and the determining of the second functional unit are performed prior to accessing the secondary opcode portion of the second instruction. 
     
     
         8 . The method of  claim 1 , wherein the providing of the third packet to the second functional unit is performed without decoding the secondary opcode portion of the second instruction. 
     
     
         9 . The method of  claim 1 , wherein the secondary opcode portion is separated from the second primary opcode portion in the first packet by a primary opcode portion of at least one other instruction. 
     
     
         10 . A circuit device comprising:
 a set of processor functional units that includes a first functional unit and a second functional unit; and   a decoder coupled to the set of processor functional units and configured to:
 receive a packet that includes:
 a first instruction that includes a first primary opcode portion; and 
 a second instruction that includes:
 a second primary opcode portion arranged adjacent to the first primary opcode portion in the packet; and 
 a secondary opcode portion separated from the second primary opcode portion in the packet; 
 
 
 determine, based on the first primary opcode portion, that the first instruction is associated with the first functional unit; 
 provide the first instruction to the first functional unit; 
 determine, based on the second primary opcode portion, that the second instruction is associated with the second functional unit; and 
 provide the second instruction to the second functional unit. 
   
     
     
         11 . The circuit device of  claim 10 , wherein:
 the first instruction includes a first size field that specifies a size of the first instruction based on the first size field and the first primary opcode portion; and   the second instruction includes a second size field that specifies a size of the second instruction based on the second size field, the second primary opcode portion, and the secondary opcode portion.   
     
     
         12 . The circuit device of  claim 11 , wherein the size of the first instruction is different from the size of the second instruction. 
     
     
         13 . The circuit device of  claim 11 , wherein:
 the first instruction includes a first link field that specifies whether the first instruction is last in the packet;   the size of the first instruction as specified by the first size field is further based on the first link field;   the second instruction includes a second link field that specifies whether the second instruction is last in the packet; and   the size of the second instruction as specified by the second size field is further based on the second link field.   
     
     
         14 . The circuit device of  claim 10 , wherein a size of the first primary opcode portion is equal to a size of the second primary opcode portion. 
     
     
         15 . The circuit device of  claim 10 , wherein the first instruction does not include a secondary opcode portion. 
     
     
         16 . The circuit device of  claim 10 , wherein the decoder is configured to determine that the first instruction is associated with the first functional unit and to determine that the second instruction is associated with the second functional unit prior to accessing the secondary opcode portion. 
     
     
         17 . The circuit device of  claim 10 , wherein the decoder is configured to provide the second instruction to the second functional unit without decoding the secondary opcode portion of the second instruction. 
     
     
         18 . The circuit device of  claim 10 , wherein the secondary opcode portion is separated from the second primary opcode portion in the packet by a primary opcode portion of at least one other instruction. 
     
     
         19 . A circuit device comprising:
 a set of processor functional units that includes a first functional unit and a second functional unit; and   a decoder coupled to the set of processor functional units and configured to:
 receive a packet that includes:
 a first portion that includes a set of primary opcode portions of a set of instructions; and 
 a second portion that includes a second of secondary opcode portions of a subset of the set of instruction, wherein the second portion and the first portion are not interleaved; 
 
 determine, based on the first portion of the packet, that a first instruction of the set of instructions is associated with the first functional unit and that a second instruction of the set of instructions is associated with the second functional unit; and 
 provide the first instruction to the first functional unit and the second instruction to the second functional unit. 
   
     
     
         20 . The circuit device of  claim 19 , wherein each primary opcode portion of the set of primary opcode portions has the same size.