Ldmos transistor and method of forming the ldmos transistor with improved rds*cgd

Abstract

The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a number of dopant implants at a number of depths, and forming a step-shaped back gate region with a number of dopant implants at a number of depths to adjoin the drain drift region.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a semiconductor substrate having a first conductivity type and a top surface;   a gate positioned above the top surface between a source region and a drain region;   a drain drift region having a second opposite conductivity type extending from the drain region toward the source region and located partially under the gate, the drain drift region having:
 a first drain drift sub-region (DDSR) near the surface and extending toward the source region a first distance; 
 a second DDSR below the first DDSR and extending toward the source region a second distance less than the first distance; and 
 a third DDSR between the first DDSR and the second DDSR and extending toward the source region a third distance greater than the second distance and less than the first distance. 
   
     
     
         2 . The integrated circuit of  claim 1 , wherein the drain drift region further includes:
 a fourth DDSR between the second and the third DDSR and extending toward the source region by a fourth distance greater than the third distance and less than the first distance.   
     
     
         3 . The integrated circuit of  claim 1 , wherein the first DDSR has a dopant concentration greater than the third dopant concentration. 
     
     
         4 . The integrated circuit of  claim 1 , wherein the first DDSR and the fourth DDSR have a dopant concentration greater than the second DDSR. 
     
     
         5 . The integrated circuit of  claim 1 , further comprising:
 a drain region above the first drain drift region and laterally spaced apart from the gate; and   an isolation structure between the drain region and the gate.   
     
     
         6 . The integrated circuit of  claim 1 , wherein the drain drift region is n-type and the substrate is p-type, further comprising:
 a first p-type region extending from the source region toward the drain region by a fifth distance and partially under the fourth DDSR;   a second p-type region located between the first p-type region and the surface and extending from the source region toward the drain region and partially under the gate by a sixth distance less than the fifth distance.   
     
     
         7 . The integrated circuit of  claim 6 , further comprising a third p-type region located under the drain drift region and the first p-type region, the third p-type region having a p-type dopant concentration greater than that of the substrate. 
     
     
         8 . A transistor, comprising:
 a p-type substrate having a top surface and a p-buried layer (PBL);   an n-type source region and an n-type drain region in the substrate and a gate electrode positioned between the source and drain regions;   an n-type drain drift region between the PBL and the drain region and extending under a first portion of the gate electrode;   a p-type body region between the PBL and the source region and extending under a second portion of the gate electrode; and   a p-type intermediate region between the PBL and the p-type body region,   wherein:
 the p-type body region extends laterally from under the source toward the drain by a first distance; 
 the p-type intermediate region extends laterally from under the source toward the drain by a second distance greater than the first distance. 
   
     
     
         9 . The transistor of  claim 8 , wherein:
 the p-type body region has a first peak horizontal dopant concentration at a first depth below the top surface, and the p-type intermediate region has a second peak horizontal dopant concentration at a second depth greater than the first depth below the top surface;   the n-type drift region has a third horizontal peak dopant concentration at a third depth below the top surface that is less than the first depth; and   the n-type drift region has a fourth horizontal peak dopant concentration at a fourth depth between the first and second depths.   
     
     
         10 . The transistor of  claim 9 , wherein the first horizontal peak dopant concentration is greater than the second horizontal peak dopant concentration. 
     
     
         11 . The transistor of  claim 8 , further comprising an isolation structure between the gate electrode and the drain region. 
     
     
         12 . The transistor of  claim 8 , wherein a portion of the n-type drift region is located between the p-type intermediate region and the gate electrode. 
     
     
         13 . The transistor of  claim 9 , wherein a portion of the n-type drift region having the fourth horizontal peak concentration is located vertically between the top surface and a portion of the intermediate region having the second horizontal peak concentration. 
     
     
         14 . A method of forming an integrated circuit, comprising:
 forming a source region and a drain region having a first conductivity type in a semiconductor substrate having a second opposite conductivity type;   forming a gate over a top surface of the substrate between the source region and the drain region;   forming under the drain region and partially under the gate a drain drift region having the first conductivity type and extending from the drain region toward the source region, the drain drift region having:
 a first drain drift sub-region (DDSR) near the surface and extending toward the source region a first distance; 
 a second DDSR below the first DDSR and extending toward the source region a second distance less than the first distance; and 
 a third DDSR between the first DDSR and the second DDSR and extending toward the source region a third distance greater than the second distance and less than the first distance. 
   
     
     
         15 . The method of  claim 14 , wherein the drain drift region further includes:
 a fourth DDSR between the second and the third DDSR and extending toward the source region by a fourth distance greater than the third distance and less than the first distance.   
     
     
         16 . The method of  claim 14 , wherein the first DDSR has a dopant concentration greater than the third dopant concentration. 
     
     
         17 . The method of  claim 14 , wherein the first DDSR and the fourth DDSR have a dopant concentration greater than the second DDSR. 
     
     
         18 . The method of  claim 14 , further comprising forming an isolation structure between the drain region and the gate. 
     
     
         19 . The method of  claim 14 , wherein the drain drift region is n-type and the substrate is p-type, further comprising:
 forming under the source region a first p-type region extending from the source region toward the drain region by a fifth distance and partially under the fourth DDSR;   forming a second p-type region located between the first p-type region and the surface and extending from the source region toward the drain region and partially under the gate by a sixth distance less than the fifth distance.   
     
     
         20 . The method of  claim 19 , further comprising forming a third p-type region located under the drain drift region and the first p-type region, the third p-type region having a p-type dopant concentration greater than that of the substrate.