US2023215871A1PendingUtilityA1

Display device and method of manufacturing the same

Assignee: SAMSUNG DISPLAY CO LTDPriority: Aug 6, 2020Filed: Mar 15, 2023Published: Jul 6, 2023
Est. expiryAug 6, 2040(~14 yrs left)· nominal 20-yr term from priority
H10D 30/0312H10D 30/0321H10D 30/6743H10D 86/421H10D 86/0221H10D 86/431H10D 86/60H10D 86/411H10D 86/427H10H 29/142H01L 29/6675G09G 3/32H10K 59/1213H10K 59/124H10K 71/00H10K 2102/351
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Claims

Abstract

A display device may include a substrate, a buffer layer on the substrate, a first active pattern on the buffer layer, the first active pattern having a first thickness, a second active pattern on the buffer layer spaced from the first active pattern and having a second thickness smaller than the first thickness, a first gate insulating layer on the first active pattern and the second active pattern, a first gate electrode on the first gate insulating layer, the first gate electrode overlapping the first active pattern, and a second gate electrode on the first gate insulating layer, the second gate electrode overlapping the second active pattern.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of manufacturing a display device, the method comprising:
 forming an amorphous silicon layer on a substrate on which a first region and a second region spaced from each other are defined;   partially etching the second region of the amorphous silicon layer;   crystallizing the amorphous silicon layer to form a polycrystalline silicon layer;   etching all regions of the polycrystalline silicon layer except for the first region and the second region to form a first polycrystalline silicon pattern and a second polycrystalline silicon pattern in the first region and the second region, respectively;   forming a first gate insulating layer on the first polycrystalline silicon pattern and the second polycrystalline silicon pattern; and   forming a first gate electrode and a second gate electrode that overlap the first polycrystalline silicon pattern and the second polycrystalline silicon pattern, respectively, on the first gate insulating layer.   
     
     
         2 . The method of  claim 1 , wherein the partially etching of the second region of the amorphous silicon layer comprises partially etching the second region of the amorphous silicon layer to a thickness greater than 0 and less than about 60 Å. 
     
     
         3 . The method of  claim 1 , wherein the forming of the amorphous silicon layer comprises forming the amorphous silicon layer to a thickness of about 300 Å to about 500 Å. 
     
     
         4 . The method of  claim 1 , further comprising washing the amorphous silicon layer with hydrofluoric acid after the partially etching of the second region of the amorphous silicon layer and before the crystallizing of the amorphous silicon layer. 
     
     
         5 . The method of  claim 1 , wherein the crystallizing of the amorphous silicon layer comprises irradiating the amorphous silicon layer by a laser having a constant energy density. 
     
     
         6 . A method of manufacturing a display device, the method comprising:
 forming a buffer layer on a substrate on which a first region and a second region spaced from each other are defined;   partially etching the first region of the buffer layer;   forming an amorphous silicon layer on the buffer layer;   polishing the amorphous silicon layer;   crystallizing the amorphous silicon layer to form a polycrystalline silicon layer;   etching all regions of the polycrystalline silicon layer except for the first region and the second region to form a first polycrystalline silicon pattern and a second polycrystalline silicon pattern in the first region and the second region, respectively;   forming a first gate insulating layer on the first polycrystalline silicon pattern and the second polycrystalline silicon pattern; and   forming a first gate electrode and a second gate electrode that overlap the first polycrystalline silicon pattern and the second polycrystalline silicon pattern, respectively, on the first gate insulating layer.   
     
     
         7 . The method of  claim 6 , wherein the polishing of the amorphous silicon layer comprises polishing the amorphous silicon layer to a thickness greater than 0 and less than about 60 Å. 
     
     
         8 . The method of  claim 6 , wherein the forming of the amorphous silicon layer comprises forming the amorphous silicon layer to a thickness of about 300 Å to about 500 Å. 
     
     
         9 . The method of  claim 6 , further comprising washing the amorphous silicon layer with hydrofluoric acid after the polishing of the amorphous silicon layer and before the crystallizing of the amorphous silicon layer. 
     
     
         10 . The method of  claim 6 , wherein the crystallizing of the amorphous silicon layer comprises irradiating the amorphous silicon layer by a laser having a constant energy density.

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