Multi-chip integrated circuit devices having recessed regions therein that support high yield dicing

Abstract

An integrated circuit device includes a semiconductor substrate having a first device region, a second device region, and a scribe line region therein. The scribe line region, which extends between the first and second device regions, includes a first edge region adjacent the first device region, a second edge region adjacent the second device region and a cutting region extending between the first and second device regions. A lower interlayer insulating layer is provided on the first and second device regions and on the scribe line region. A first multi-level guard ring is provided, which at least partially surrounds the first device region, when viewed from a plan perspective. An insulating structure is provided, which has a recess therein. The recess extends adjacent the first multi-level guard rings and exposes an upper surface of the lower interlayer insulating layer.

1 . An integrated circuit device, comprising:
 a semiconductor substrate including a first device region, a second device region, and a scribe line region extending between the first and second device regions, said scribe line region comprising a first edge region adjacent the first device region, a second edge region adjacent the second device region and a cutting region extending between the first and second device regions;   a lower interlayer insulating layer on the first and second device regions and on the scribe line region;   a first multi-level guard ring at least partially surrounding the first device region, when viewed from a plan perspective;   a second multi-level guard ring at least partially surrounding the second device region, when viewed from the plan perspective; and   an insulating structure having a recess therein, which extends between the first and second multi-level guard rings and exposes an upper surface of the lower interlayer insulating layer.   
     
     
         2 . The device of  claim 1 , wherein the recess exposes a portion of the upper surface of the lower interlayer insulating layer extending opposite the cutting region. 
     
     
         3 . The device of  claim 1 , wherein a first portion of the first multi-level guard ring extends within the lower interlayer insulating layer, and a second portion of the first multi-level guard ring extends on an upper surface of the lower interlayer insulating layer. 
     
     
         4 . The device of  claim 1 , further comprising a first multi-level dam structure extending between the first multi-level guard ring and the recess in the insulating structure. 
     
     
         5 . The device of  claim 1 , wherein a minimum width of the recess is greater than a width of the cutting region, when viewed from the plan perspective. 
     
     
         6 . The device of  claim 1 , wherein the semiconductor substrate includes a structurally-weakened region therein, which is aligned to the cutting region. 
     
     
         7 . The device of  claim 6 , wherein the structurally-weakened region is a laser-irradiated region. 
     
     
         8 . The device of  claim 1 , wherein the insulating structure comprises a lower insulating structure on the lower interlayer insulating layer and an upper insulating structure on the lower insulating structure; and wherein a first width of the recess in the upper insulating structure is greater than a second width of the recess in the lower insulating structure. 
     
     
         9 . The device of  claim 8 , wherein the second width of the recess is greater than a width of the cutting region; and wherein a width of the scribe line region is greater than the first width of the recess. 
     
     
         10 . The device of  claim 8 , wherein a spacing between the first and second multi-level guard rings is greater than the first width of the recess. 
     
     
         11 . (canceled) 
     
     
         12 . The device of  claim 24 , wherein a horizontal length of an upper surface of a portion of the lower interlayer insulating layer exposed by the first recessed region is in a range from 15 μm to 17 μm. 
     
     
         13 . The device of  claim 24 , wherein the side surface of a lowermost one of the lower insulating layers is rounded. 
     
     
         14 . The device of  claim 24 ,
 wherein a side surface of the semiconductor substrate is coplanar with a side surface of the lower interlayer insulating layer; and   wherein a side surface of the lower insulating structure is nearer to the device region than the side surface of the lower interlayer insulating layer.   
     
     
         15 .- 23 . (canceled) 
     
     
         24 . An integrated circuit device, comprising:
 a semiconductor substrate including a device region, and an edge region surrounding the device region;   a device layer on the semiconductor substrate, said device layer including a lower interlayer insulating layer covering the semiconductor substrate;   an insulating structure including a lower insulating structure on the device layer, and an upper insulating structure on the lower insulating structure, said lower insulating structure including lower insulating layers stacked on the lower interlayer insulating layer;   a protective layer on the upper insulating structure;   a passivation layer on the protective layer; and   a crack prevention structure formed in an opening vertically extending through the insulating structure in the edge region;   wherein the insulating structure includes a first recessed region, which is formed at an edge of the device layer in the edge region and exposes an upper surface of the lower interlayer insulating layer and side surfaces of the lower insulating layers; and   wherein the upper insulating structure includes a second recessed region formed over the first recessed region and nearer to the device region than the first recessed region.   
     
     
         25 . The device of  claim 24 ,
 wherein the upper insulating structure includes a first upper insulating layer, a second upper insulating layer and a third upper insulating layer sequentially stacked;   wherein the third upper insulating layer includes a first portion, and a second portion connected to the first portion and smaller in thickness than the first portion; and   wherein the crack prevention structure extends from an upper surface of the second portion to the device layer.   
     
     
         26 . The device of  claim 24 , wherein the crack prevention structure includes:
 a first material layer covering an inner wall of the opening;   a second material layer covering the first material layer; and   a third material layer covering the second material layer and filling the opening.   
     
     
         27 . The device of  claim 26 , wherein the second material layer is formed to be integrated with the protective layer; and wherein the third material layer is formed to be integrated with the passivation layer. 
     
     
         28 . The device of  claim 24 , further comprising:
 dam structures within the lower insulating structure, in the edge region; and   wherein the carack prevention structure extends among the dam structures.   
     
     
         29 . A packaged integrated circuit device, comprising:
 a package substrate including an upper pad and an outer connection terminal, said upper pad extending on an upper surface of the package substrate, and the outer connecting terminal being a lower surface of the package substrate;   a semiconductor chip on the package substrate;   a bonding wire connecting the semiconductor chip to the upper pad;   an adhesive member extending between the package substrate and the semiconductor chip; and   an encapsulant covering the package substrate and the semiconductor chip;   wherein the semiconductor chip includes:
 a semiconductor substrate including a device region, and an edge region surrounding the device region; 
 a device layer extending on the semiconductor substrate, the device layer including a lower interlayer insulating layer covering the semiconductor substrate, an insulating structure including a lower insulating structure on the device layer, and an upper insulating structure on the lower insulating structure, the lower insulating structure including lower insulating layers stacked on the lower interlayer insulating layer, and 
 a protective layer on the upper insulating structure, and a passivation layer on the protective layer; 
   wherein the insulating structure includes a first recessed region, which is formed at an edge of the device layer in the edge region and exposes an upper surface of the lower interlayer insulating layer and side surfaces of the lower insulating layers; and   wherein the upper insulating structure includes a second recessed region formed over the first recessed region and nearer to the device region than the first recessed region.   
     
     
         30 . The device of  claim 29 , wherein the semiconductor chip further includes a chip pad in the upper insulating structure, a connection pad on the chip pad, and the protective layer partially covers the connection pad; and wherein the connection pad is connected to the bonding wire. 
     
     
         31 .- 35 . (canceled)