Cache memory system and cache memory control method

Abstract

According to one embodiment, a cache memory system includes a cache memory and a cache controller. The cache memory can store first data to be read or written by a processor. The cache controller is configured to execute a refresh. The refresh includes reading the first data stored in the cache memory and writing the read first data to the cache memory. When executing the refresh, the cache controller is configured to exchange the first data stored in a first area of the cache memory for second data stored in a second area of the cache memory.

What is claimed is: 
     
         1 . A cache memory system comprising:
 a cache memory capable of storing first data to be read or written by a processor; and   a cache controller configured to execute a refresh, the refresh including reading the first data stored in the cache memory and writing the read first data to the cache memory, wherein 
 the cache memory includes a plurality of cache lines, 
 each of the plurality of cache lines is specified by one of a plurality of indexes and one of a plurality of ways, 
 each of a plurality of cache lines corresponding to each of the plurality of indexes is specified by each of the plurality of ways, 
 when executing the refresh, the cache controller is configured to exchange the first data stored in a first cache line of the plurality of cache lines for second data stored in a second cache line of the plurality of cache, 
 the first cache line corresponds to a first index of the plurality of indexes and a first way of the plurality of ways, and 
 the second cache line corresponds to a second index of the plurality of indexes and a second way of the plurality of ways, the second way being different from the first way. 
   
     
     
         2 . The cache memory system according to  claim 1 , wherein 
 the cache memory includes the first cache line and the second cache line to which the first index corresponds and includes a third cache line and a fourth cache line to which the second index corresponds, and   when an information processing device including the processor is activated or when the information processing device returns from a sleep state, the cache controller is configured to make the second index correspond to the first cache line and the second cache line, and make a third index correspond to the third cache line and the fourth cache line.   
     
     
         3 . The cache memory system according to  claim 2 , wherein 
 when receiving a read request or a write request and an address from the processor, the cache controller is configured to read data from the cache memory or write data to the cache memory by using an index derived from the address.   
     
     
         4 . The cache memory system according to  claim 1 , wherein 
 the cache controller is configured to manage first deterioration information corresponding to the first cache line and second deterioration information corresponding to the second cache line, and select the first cache line and the second cache line for exchange based on the first deterioration information and the second deterioration information.   
     
     
         5 . The cache memory system according to  claim 4 , wherein 
 the first deterioration information is the number of times of first write for the first cache line,   the second deterioration information is the number of times of second write for the second cache line, and   the cache controller is configured to select the first cache line as an exchange source in a case where the number of times of the first write is equal to or more than a first threshold, and select the second cache line as an exchange destination in a case where the number of times of the second write is equal to or less than a second threshold.   
     
     
         6 . The cache memory system according to  claim 1 , wherein 
 the cache controller is configured to manage the number of times of write for each of the cache lines, select the first cache line with a maximum number of times of write as an exchange source among the cache lines to which the first index corresponds, and select the second cache line with a minimum number of times of write as the exchange destination among the cache lines to which the first index corresponds.   
     
     
         7 . The cache memory system according to  claim 1 , wherein 
 the cache controller is configured to:   manage a plurality of pieces of deterioration information for each of a plurality of cache lines of the cache memory; and   select the first cache line and the second cache line for exchange based on the pieces of deterioration information.   
     
     
         8 . The cache memory system according to  claim 1 , wherein 
 the cache controller is configured to: 
 select the first cache line and the second cache line and execute a refresh of exchange the first data for the second data in a case where a condition for determining whether or not to perform the exchange is satisfied; and 
 execute a refresh of writing the first data stored in the first cache line in the cache memory to the first cache line in a case where the condition is not satisfied. 
   
     
     
         9 . The cache memory system according to  claim 1 , wherein 
 in a case where the first data is written to a write unit area of the cache memory, the cache controller reads third data corresponding to the write unit area from the main memory, writes the third data to the write unit area of the cache memory, and executes a read-modify-write for updating the write unit area with the first data received from the processor.   
     
     
         10 . The cache memory system according to  claim 1 , wherein 
 the cache controller is configured to write the first data including a tag which is an identifier of data stored in a cache line, valid information, update information, history information, and the data to a cache line of the cache memory.   
     
     
         11 . The cache memory system according to  claim 1 , wherein 
 the cache memory includes a first table and a second table,   the first table is a table for managing tag information including a tag which is an identifier of data stored in a cache line included in the cache memory, valid information, update information, and history information, and   the second table is a table for managing the data corresponding to the tag information.   
     
     
         12 . The cache memory system according to  claim 11 , wherein 
 in a case where the data is moved in the second table, the cache memory moves the tag information to a position corresponding to a movement destination of the data in the first table.   
     
     
         13 . The cache memory system according to  claim 11 , wherein 
 in a case where the tag information is moved in the first table, the cache memory moves the data to a position corresponding to a movement destination of the tag information in the second table.   
     
     
         14 . The cache memory system according to  claim 1 , wherein the cache memory is an N-way set-associative cache memory.