Manufacturing method of semiconductor device and semiconductor device

Abstract

First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;   a drift layer of a first conductivity type formed over the semiconductor substrate;   a channel layer of a second conductivity type opposite to the first conductivity type formed on the drift layer;   a source region of the first conductivity type formed on the channel layer;   a trench penetrating the source region and the channel layer to reach the drift layer;   a gate electrode embedded in the trench via a gate insulating film;   a first semiconductor region of the second conductivity type formed in the drift layer such that the first semiconductor region contacts a bottom surface of the trench;   a second semiconductor region of the second conductivity type formed in the drift layer at a first side of the first semiconductor region in plan view; and   a third semiconductor region of the second conductivity type formed in the drift layer at a second side opposite to the first side of the first semiconductor region in plan view, wherein   the second semiconductor region and the third semiconductor region are separate apart from the first semiconductor region.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the first semiconductor region and the bottom surface of the trench are overlapped in plan view. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein
 a first distance between the second semiconductor region and the trench in plan view and a second distance between the third semiconductor region and the trench in plan view are approximately same.   
     
     
         4 . The semiconductor device according to  claim 1 , wherein
 the second semiconductor region and the third semiconductor region are separate apart from the channel layer.   
     
     
         5 . The semiconductor device according to  claim 1 , further comprising:
 a body contact region of the second conductivity type formed in the source region and the channel layer, wherein   one end of the source region contacts the trench, and other end of the source region contacts the body contact region.   
     
     
         6 . The semiconductor device according to  claim 5 , wherein
 an impurity concentration of the body contact region is higher than an impurity concentration of the channel layer.   
     
     
         7 . The semiconductor device according to  claim 1 , wherein
 the drift layer, the channel layer, the source region, the first semiconductor region, the second semiconductor region and the third semiconductor region are configured by SiC.   
     
     
         8 . The semiconductor device according to  claim 1 , further comprising:
 an interlayer insulating film formed on the gate electrode; and   a contact hole formed in the interlayer insulating film;   a source electrode formed on the interlayer insulating film and in the contact hole,   a drain electrode formed on the second main surface, wherein   the gate electrode, the source electrode and the drain electrode configure a transistor.