Efficient circuit for neural network processing

Abstract

A system and method for efficient processing for neural network inference operations. In some embodiments, the system includes: a circuit configured to multiply a first number by a second number, the first number being represented as: a sign bit five exponent bits, and seven mantissa bits, representing an eight-bit full mantissa.

What is claimed is: 
     
         1 . A system, comprising:
 a circuit configured to multiply a first number by a second number,   the first number being represented as:
 a sign bit 
 five exponent bits, and 
 seven mantissa bits, representing an eight-bit full mantissa. 
   
     
     
         2 . The system of  claim 1 , wherein the circuit comprises:
 a first multiplier;   a second multiplier;   a third multiplier; and   a fourth multiplier,   each of the first multiplier, the second multiplier, the third multiplier, and the fourth multiplier being a 4 bit by 8 bit multiplier.   
     
     
         3 . The system of  claim 2 , wherein the second number is represented as:
 a sign bit   five exponent bits, and   seven mantissa bits, representing an eight-bit full mantissa.   
     
     
         4 . The system of  claim 3 , wherein the circuit is configured, in a first configuration, to multiply the mantissa of the first number and the mantissa of the second number using the first multiplier and the second multiplier. 
     
     
         5 . The system of  claim 4 , wherein the circuit is configured, in a second configuration, to calculate an approximate product of a third number and a fourth number, each of the third number and the fourth number being represented as:
 a sign bit   five exponent bits, and   ten mantissa bits, representing an 11-bit full mantissa.   
     
     
         6 . The system of  claim 5 , wherein the circuit is configured, in the second configuration, to:
 multiply eight bits of the full mantissa of the third number by eight bits of the full mantissa of the fourth number using the first multiplier and the second multiplier,   multiply three bits of the full mantissa of the third number by eight bits of the full mantissa of the fourth number using the third multiplier, and   multiply eight bits of the full mantissa of the third number by three bits of the full mantissa of the fourth number using the fourth multiplier.   
     
     
         7 . The system of  claim 6 , wherein the circuit is configured not to calculate the product of the three least significant bits of the full mantissa of the third number and the three least significant bits of the full mantissa of the fourth number. 
     
     
         8 . The system of  claim 2 , wherein the second number is an 8-bit integer and the circuit is configured to multiply 8 bits of the full mantissa of the first number by the second number using the first multiplier and the second multiplier. 
     
     
         9 . The system of  claim 2 , wherein the second number is a 4-bit integer and the circuit is configured to multiply 8 bits of the full mantissa of the first number by the second number using the first multiplier. 
     
     
         10 . A method comprising:
 multiplying, by a circuit, a first number by a second number, the first number being represented as:
 a sign bit 
 five exponent bits, and 
 seven mantissa bits, representing an eight-bit full mantissa. 
   
     
     
         11 . The method of  claim 10 , wherein the circuit comprises:
 a first multiplier;   a second multiplier;   a third multiplier; and   a fourth multiplier,   each of the first multiplier, the second multiplier, the third multiplier, and the fourth multiplier being a 4 bit by 8 bit multiplier.   
     
     
         12 . The method of  claim 11 , wherein the second number is represented as:
 a sign bit   five exponent bits, and   seven mantissa bits, representing an eight-bit full mantissa.   
     
     
         13 . The method of  claim 12 , wherein the circuit is configured, in a first configuration, to multiply the mantissa of the first number and the mantissa of the second number using the first multiplier and the second multiplier. 
     
     
         14 . The method of  claim 13 , wherein the circuit is configured, in a second configuration, to calculate an approximate product of a third number and a fourth number, each of the third number and the fourth number being represented as:
 a sign bit   five exponent bits, and   ten mantissa bits, representing an 11-bit full mantissa.   
     
     
         15 . The method of  claim 14 , wherein the circuit is configured, in the second configuration, to:
 multiply eight bits of the full mantissa of the third number by eight bits of the full mantissa of the fourth number using the first multiplier and the second multiplier,   multiply three bits of the full mantissa of the third number by eight bits of the full mantissa of the fourth number using the third multiplier, and   multiply eight bits of the full mantissa of the third number by three bits of the full mantissa of the fourth number using the fourth multiplier.   
     
     
         16 . The method of  claim 15 , wherein the circuit is configured not to calculate the product of the three least significant bits of the full mantissa of the third number and the three least significant bits of the full mantissa of the fourth number. 
     
     
         17 . The method of  claim 11 , wherein the second number is an 8-bit integer and the circuit is configured to multiply 8 bits of the full mantissa of the first number by the second number using the first multiplier and the second multiplier. 
     
     
         18 . The method of  claim 11 , wherein the second number is a 4-bit integer and the circuit is configured to multiply 8 bits of the full mantissa of the first number by the second number using the first multiplier. 
     
     
         19 . A system, comprising:
 means for multiplying a first number by a second number,   the first number being represented as:
 a sign bit 
 five exponent bits, and 
 seven mantissa bits, representing an eight-bit full mantissa. 
   
     
     
         20 . The system of  claim 19 , wherein the means for multiplying comprises:
 a first multiplier;   a second multiplier;   a third multiplier; and   a fourth multiplier,   each of the first multiplier, the second multiplier, the third multiplier, and the fourth multiplier being a 4 bit by 8 bit multiplier.