Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first stacked structure including first conductive layers and first insulating layers stacked alternately with the first conductive layers;   a second stacked structure including second conductive layers and second insulating layers stacked alternately with the second conductive layers, wherein the second stacked structure is located under the first stacked structure;   a third insulating layer between the first stacked structure and the second stacked structure;   first semiconductor patterns passing through the first stacked structure; and   second semiconductor patterns passing through the second stacked structure;   wherein each of bottoms of the first semiconductor patterns is adjacent to the third insulating layer and has a first outer diameter,   wherein each of tops of the second semiconductor patterns is adjacent to the third insulating layer and has a second outer diameter, and   wherein the first outer diameter is smaller than the second outer diameter.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising a coupling pattern disposed between adjacent first and second semiconductor patterns among the first semiconductor patterns and the second semiconductor patterns. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the coupling pattern and the adjacent first and second semiconductor patterns are connected to each other to form a channel layer. 
     
     
         4 . The semiconductor device of  claim 2 , wherein the coupling pattern is formed in the third insulating layer. 
     
     
         5 . The semiconductor device of  claim 2 , wherein the coupling pattern includes a sidewall protruding farther than a sidewall of each of the first and second semiconductor patterns in a lateral direction. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising multilayer dielectric layers surrounding sidewalls of the first and second semiconductor patterns. 
     
     
         7 . The semiconductor device of  claim 6 , wherein each of the multilayer dielectric layers includes a tunnel insulating layer, a data storage layer and a charge blocking layer. 
     
     
         8 . A semiconductor device, comprising:
 a first stacked structure including first conductive layers and first insulating layers stacked alternately with the first conductive layers;   a second stacked structure including second conductive layers and second insulating layers stacked alternately with the second conductive layers, wherein the second stacked structure is located under the first stacked structure;   a third insulating layer between the first stacked structure and the second stacked structure;   first semiconductor patterns passing through the first stacked structure; and   second semiconductor patterns passing through the second stacked structure,   wherein the first insulating layers include a lower first insulating layer adjacent to the third insulating layer,   wherein the second insulating layers include an upper second insulating layer adjacent to the third insulating layer, and   wherein the lower first insulating layer on a sidewall of each of the first semiconductor patterns is wider than the upper second insulating layer on a sidewall of each of the second semiconductor patterns.   
     
     
         9 . The semiconductor device of  claim 8 , further comprising a coupling pattern disposed between adjacent first and second semiconductor patterns among the first semiconductor patterns and the second semiconductor patterns. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the coupling pattern and the adjacent first and second semiconductor patterns are connected to each other to form a channel layer. 
     
     
         11 . The semiconductor device of  claim 9 , wherein the coupling pattern is formed in the third insulating layer. 
     
     
         12 . The semiconductor device of  claim 9 , wherein the coupling pattern includes a sidewall protruding farther than a sidewall of each of the first and second semiconductor patterns in a lateral direction. 
     
     
         13 . The semiconductor device of  claim 8 , further comprising multilayer dielectric layers surrounding sidewalls of the first and second semiconductor patterns. 
     
     
         14 . The semiconductor device of  claim 13 , wherein each of the multilayer dielectric layers includes a tunnel insulating layer, a data storage layer and a charge blocking layer.